start_rvds.s

RT-Thread是发展中的下一代微内核嵌入式实时操作系统

                LDR     R1, =RSTC_MR_Val
                STR     R1, [R0, #RSTC_MR]
                ENDIF


; Setup EFC0
                IF      EFC0_SETUP != 0
                LDR     R0, =EFC_BASE
                LDR     R1, =EFC0_FMR_Val
                STR     R1, [R0, #EFC0_FMR]
                ENDIF

; Setup EFC1
                IF      EFC1_SETUP != 0
                LDR     R0, =EFC_BASE
                LDR     R1, =EFC1_FMR_Val
                STR     R1, [R0, #EFC1_FMR]
                ENDIF

; Setup WDT
                IF      WDT_SETUP != 0
                LDR     R0, =WDT_BASE
                LDR     R1, =WDT_MR_Val
                STR     R1, [R0, #WDT_MR]
                ENDIF


; Setup PMC
                IF      PMC_SETUP != 0
                LDR     R0, =PMC_BASE

;  Setup Main Oscillator
                LDR     R1, =PMC_MOR_Val
                STR     R1, [R0, #PMC_MOR]

;  Wait until Main Oscillator is stablilized
                IF      (PMC_MOR_Val:AND:PMC_MOSCEN) != 0
MOSCS_Loop      LDR     R2, [R0, #PMC_SR]
                ANDS    R2, R2, #PMC_MOSCS
                BEQ     MOSCS_Loop
                ENDIF

;  Setup the PLL
                IF      (PMC_PLLR_Val:AND:PMC_MUL) != 0
                LDR     R1, =PMC_PLLR_Val
                STR     R1, [R0, #PMC_PLLR]

;  Wait until PLL is stabilized
PLL_Loop        LDR     R2, [R0, #PMC_SR]
                ANDS    R2, R2, #PMC_LOCK
                BEQ     PLL_Loop
                ENDIF

;  Select Clock
                IF      (PMC_MCKR_Val:AND:PMC_CSS) == 1     ; Main Clock Selected
                LDR     R1, =PMC_MCKR_Val
                AND     R1, #PMC_CSS
                STR     R1, [R0, #PMC_MCKR]
WAIT_Rdy1       LDR     R2, [R0, #PMC_SR]
                ANDS    R2, R2, #PMC_MCKRDY
                BEQ     WAIT_Rdy1
                LDR     R1, =PMC_MCKR_Val
                STR     R1, [R0, #PMC_MCKR]
WAIT_Rdy2       LDR     R2, [R0, #PMC_SR]
                ANDS    R2, R2, #PMC_MCKRDY
                BEQ     WAIT_Rdy2
                ELIF    (PMC_MCKR_Val:AND:PMC_CSS) == 3     ; PLL  Clock Selected
                LDR     R1, =PMC_MCKR_Val
                AND     R1, #PMC_PRES
                STR     R1, [R0, #PMC_MCKR]
WAIT_Rdy1       LDR     R2, [R0, #PMC_SR]
                ANDS    R2, R2, #PMC_MCKRDY
                BEQ     WAIT_Rdy1
                LDR     R1, =PMC_MCKR_Val
                STR     R1, [R0, #PMC_MCKR]
WAIT_Rdy2       LDR     R2, [R0, #PMC_SR]
                ANDS    R2, R2, #PMC_MCKRDY
                BEQ     WAIT_Rdy2
                ENDIF   ; Select Clock
                ENDIF   ; PMC_SETUP


; Copy Exception Vectors to Internal RAM

                IF      :DEF:RAM_INTVEC
                ADR     R8, Vectors         ; Source
                LDR     R9, =RAM_BASE       ; Destination
                LDMIA   R8!, {R0-R7}        ; Load Vectors 
                STMIA   R9!, {R0-R7}        ; Store Vectors 
                LDMIA   R8!, {R0-R7}        ; Load Handler Addresses 
                STMIA   R9!, {R0-R7}        ; Store Handler Addresses
                ENDIF


; Remap on-chip RAM to address 0

MC_BASE EQU     0xFFFFFF00      ; MC Base Address
MC_RCR  EQU     0x00            ; MC_RCR Offset

                IF      :DEF:REMAP
                LDR     R0, =MC_BASE
                MOV     R1, #1
                STR     R1, [R0, #MC_RCR]   ; Remap
                ENDIF


; Setup Stack for each mode

                LDR     R0, =Stack_Top

;  Enter Undefined Instruction Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #UND_Stack_Size

;  Enter Abort Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #ABT_Stack_Size

;  Enter FIQ Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #FIQ_Stack_Size

;  Enter IRQ Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #IRQ_Stack_Size

;  Enter Supervisor Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
                MOV     SP, R0
                SUB     R0, R0, #SVC_Stack_Size

;  Enter User Mode and set its Stack Pointer
                ; MSR     CPSR_c, #Mode_USR
                IF      :DEF:__MICROLIB

                EXPORT __initial_sp

                ELSE

                MOV     SP, R0
                SUB     SL, SP, #USR_Stack_Size

                ENDIF


; Enter the C code

                IMPORT  __main
                LDR     R0, =__main
                BX      R0

				IMPORT rt_interrupt_enter
				IMPORT rt_interrupt_leave
				IMPORT rt_thread_switch_interrput_flag
				IMPORT rt_interrupt_from_thread
				IMPORT rt_interrupt_to_thread
				IMPORT rt_hw_trap_irq
				
IRQ_Handler		PROC
				EXPORT IRQ_Handler
				stmfd	sp!, {r0-r12,lr}
				bl	rt_interrupt_enter
				bl	rt_hw_trap_irq
				bl	rt_interrupt_leave

				; if rt_thread_switch_interrput_flag set, jump to
				; rt_hw_context_switch_interrupt_do and don't return
				ldr	r0, =rt_thread_switch_interrput_flag
				ldr	r1, [r0]
				cmp	r1, #1
				beq	rt_hw_context_switch_interrupt_do

				ldmfd	sp!, {r0-r12,lr}
				subs	pc, lr, #4
				ENDP

; /*
; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
; */
rt_hw_context_switch_interrupt_do	PROC
				EXPORT rt_hw_context_switch_interrupt_do
				mov	r1,  #0				; clear flag
				str	r1,  [r0]

				ldmfd	sp!, {r0-r12,lr}; reload saved registers
				stmfd	sp!, {r0-r3}	; save r0-r3
				mov	r1,  sp
				add	sp,  sp, #16		; restore sp
				sub	r2,  lr, #4			; save old task's pc to r2

				mrs	r3,  spsr			; disable interrupt
				orr	r0,  r3, #I_Bit|F_Bit
				msr	spsr_c, r0

				; switch to SVC mode 
                MSR     cpsr_c, #Mode_SVC
				; ldr	r0,  =.+8			; switch to interrupted task's stack
				; movs pc,  r0

				stmfd	sp!, {r2}		; push old task's pc
				stmfd	sp!, {r4-r12,lr}; push old task's lr,r12-r4
				mov	r4,  r1				; Special optimised code below
				mov	r5,  r3
				ldmfd	r4!, {r0-r3}
				stmfd	sp!, {r0-r3}	; push old task's r3-r0
				stmfd	sp!, {r5}		; push old task's psr
				mrs	r4,  spsr
				stmfd	sp!, {r4}		; push old task's spsr

				ldr	r4,  =rt_interrupt_from_thread
				ldr	r5,  [r4]
				str	sp,  [r5]			; store sp in preempted tasks's TCB
			
				ldr	r6,  =rt_interrupt_to_thread
				ldr	r6,  [r6]
				ldr	sp,  [r6]			; get new task's stack pointer
			
				ldmfd	sp!, {r4}		; pop new task's spsr
				msr	SPSR_cxsf, r4
				ldmfd	sp!, {r4}		; pop new task's psr
				msr	CPSR_cxsf, r4
			
				ldmfd	sp!, {r0-r12,lr,pc}	; pop new task's r0-r12,lr & pc
				ENDP

                IF      :DEF:__MICROLIB

                EXPORT  __heap_base
                EXPORT  __heap_limit

                ELSE
; User Initial Stack & Heap
                AREA    |.text|, CODE, READONLY

                IMPORT  __use_two_region_memory
                EXPORT  __user_initial_stackheap
__user_initial_stackheap

                LDR     R0, =  Heap_Mem
                LDR     R1, =(Stack_Mem + USR_Stack_Size)
                LDR     R2, = (Heap_Mem +      Heap_Size)
                LDR     R3, = Stack_Mem
                BX      LR
                ENDIF

                END