start.s

RT-Thread是发展中的下一代微内核嵌入式实时操作系统

/*
 * File      : start.S
 * This file is part of RT-Thread RTOS
 * COPYRIGHT (C) 2006, RT-Thread Development Team
 *
 * The license and distribution terms for this file may be
 * found in the file LICENSE in this distribution or at
 * http://openlab.rt-thread.com/license/LICENSE
 *
 * Change Logs:
 * Date           Author       Notes
 * 2006-08-17     Vai      first version
 */

/**
 * @addtogroup nds
 */
/*@{*/
#define CONFIG_STACKSIZE 8192

#define I_BIT       0x00000080
#define F_BIT       0x00000040
#define T_BIT       0x00000020

/* Area Size -- ref ARM946E-S */
#define PAGE_4K     (0b01011 << 1)
#define PAGE_8K     (0b01100 << 1)
#define PAGE_16K    (0b01101 << 1)
#define PAGE_32K    (0b01110 << 1)
#define PAGE_64K    (0b01111 << 1)
#define PAGE_128K   (0b10000 << 1)
#define PAGE_256K   (0b10001 << 1)
#define PAGE_512K   (0b10010 << 1)
#define PAGE_1M	    (0b10011 << 1)
#define PAGE_2M	    (0b10100 << 1)
#define PAGE_4M	    (0b10101 << 1)
#define PAGE_8M	    (0b10110 << 1)
#define PAGE_16M    (0b10111 << 1)
#define PAGE_32M    (0b11000 << 1)
#define PAGE_64M    (0b11001 << 1)
#define PAGE_128M   (0b11010 << 1)
#define PAGE_256M   (0b11011 << 1)
#define PAGE_512M   (0b11100 << 1)
#define PAGE_1G	    (0b11101 << 1)
#define PAGE_2G     (0b11110 << 1)
#define PAGE_4G     (0b11111 << 1)

/*
 *	Start address of the DTCM Memory.
 */
#define DTCM_BASE   0x027C0000  /* NDS DTCM standard address */

#define SVC_MODE    0x00000013


.text

.global _start
_start:
	b	reset
	ldr	pc, _vector_undef
	ldr	pc, _vector_swi
	ldr	pc, _vector_pabt
	ldr	pc, _vector_dabt
	ldr	pc, _vector_resv
	ldr	pc, _vector_irq
	ldr	pc, _vector_fiq

_vector_undef:	.word vector_undef
_vector_swi:	.word vector_swi
_vector_pabt:	.word vector_pabt
_vector_dabt:	.word vector_dabt
_vector_resv:	.word vector_resv
_vector_irq:	.word vector_irq
_vector_fiq:	.word vector_fiq

	.balignl 16,0xdeadbeef


/*
 * These are defined in the board-specific linker script.
 */

.globl _rtthread_start
_rtthread_start:.word _start
.globl _rtthread_end
_rtthread_end:	.word  _end
 
.globl _bss_start
_bss_start:
	.word __bss_start

.globl _bss_end
_bss_end:
	.word _end

_TEXT_BASE:
    .word   TEXT_BASE
	
/* DTCM region */
_STACK_BASE:
    .word   (DTCM_BASE + 0x4000)

reset:
    mov     r0, #F_BIT | I_BIT | SVC_MODE
    msr     cpsr_c, r0

    /* enable ARM9 IWRAM */
    mov     r0, #0x04000000
    mov     r1, #0
    strb    r1, [r0, #0x247]

    ldr     r0, =0x04000204
    ldrh    r1, [r0]
    bic     r1, r1, #0x0080
    bic     r1, r1, #0x8800
    strh    r1, [r0]

    /* Disable I-Cache & D-Cache */
    mov     r0, #0
    mcr     p15, 0, r0, c7, c5, 0
    mcr     p15, 0, r0, c7, c6, 0

    /* Wait for write buffer to empty */
    mcr     p15, 0, r0, c7, c10, 4

    ldr     r0, =(DTCM_BASE | 0x0a)
    mcr     p15, 0, r0, c9, c1

    /* Setup memory regions */

    /* Region 0 - ITCM */
    ldr     r0, =(PAGE_32K | 0x00000000 | 1)
    mcr     p15, 0, r0, c6, c0, 0

    /* Region 1 - Main Memory */
    ldr     r0, =(PAGE_4M | 0x02000000 | 1)
    mcr     p15, 0, r0, c6, c1, 0

    /* Region 2 - DTCM */
    ldr     r0, =(PAGE_16K | DTCM_BASE | 1)
    mcr     p15, 0, r0, c6, c2, 0

    /* Region 3 - IWRAM */
    ldr     r0, =(PAGE_32K | 0x037F8000 | 1)
    mcr     p15, 0, r0, c6, c3, 0

    /* Region 4 - I/O and Kernel Video RAM */
    ldr     r0, =(PAGE_64M | 0x04000000 | 1)
    mcr     p15, 0, r0, c6, c4, 0

    /* Region 5 - User-accessible Video-RAM */
    ldr     r0, =(PAGE_16M | 0x06000000 | 1)
    mcr     p15, 0, r0, c6, c5, 0

    /* Region 6 - GBA SLOT ROM for I/O access */
    ldr     r0, =(PAGE_64M | 0x08000000 | 1)
    mcr     p15, 0, r0, c6, c6, 0

    /* Region 7 - GBA SLOT ROM for Program + Data */
    ldr     r0, =(PAGE_32M | 0x08000000 | 1)
    mcr     p15, 0, r0, c6, c7, 0

    /* Write buffer enable */
    ldr     r0, =0b11111010
    mcr     p15, 0, r0, c3, c0, 0

    /* D-cache enable */
    ldr     r0, =0b00000010
    mcr     p15, 0, r0, c2, c0, 0

    /* I-cache enable */
    ldr     r0, =0b10000010
    mcr     p15, 0, r0, c2, c0, 1

    /* IAccess */
    ldr     r0, =0x60000065
    mcr     p15, 0, r0, c5, c0, 3

    /* DAccess */
    ldr     r0, =0x31311331
    mcr     p15, 0, r0, c5, c0, 2

    /* Enable ICache, DCache, ITCM & DTCM. Set round-robin-replacement */
    mrc     p15, 0, r0, c1, c0, 0
    ldr     r1, =0x55005
    orr     r0, r0, r1
    ldr     r1, =0xfdfff
    and     r0, r0, r1
    mcr     p15, 0, r0, c1, c0, 0


	/* set exception vector */
	ldr	r0, _TEXT_BASE		/* source address 0x8000 */
	mov r1, #0x00			/* target address 0x00   */
	add	r2, r0, #0x20		/* size, 32bytes         */

copy_loop:
	ldmia	r0!, {r3-r10}	/* copy from source address [r0]    */
	stmia	r1!, {r3-r10}	/* copy to   target address [r1]    */
	cmp	r0, r2				/* until source end addreee [r2]    */
	ble	copy_loop

	/* Set up the stack						    */
	ldr	    r0, _STACK_BASE
	sub	    sp, r0, #12

	/* start RT-Thread Kernel */
	ldr	pc, _rtthread_startup

_rtthread_startup: .word rtthread_startup





/* exception handlers */
/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */

@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52
#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define USERMODE	0x10
#define FIQMODE		0x11
#define IRQMODE		0x12
#define SVCMODE		0x13
#define ABORTMODE	0x17
#define UNDEFMODE	0x1b
#define MODEMASK	0x1f
#define NOINT		0xc0

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 */
	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}		@ Calling r0-r12
	add     r8, sp, #S_PC

	ldr	r2, _rtthread_end
	add	r2, r2, #CONFIG_STACKSIZE
	sub	r2, r2, #8
	ldmia	r2, {r2 - r4}		@ get pc, cpsr, old_r0
	add	r0, sp, #S_FRAME_SIZE	@ restore sp_SVC

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r4}		@ save sp_SVC, lr_SVC, pc, cpsr, old_r
	mov	r0, sp
	.endm

	.macro	get_bad_stack
	ldr	r13, _rtthread_end		@ setup our mode stack
	add	r13, r13, #CONFIG_STACKSIZE	@ resides at top of normal stack
	sub	r13, r13, #8

	str	lr, [r13]				@ save caller lr / spsr
	mrs	lr, spsr
	str     lr, [r13, #4]

	mov	r13, #SVCMODE			@ prepare SVC-Mode
	msr	spsr_c, r13
	mov	lr, pc
	movs	pc, lr
	.endm

/* exception handlers */
	.align  5
vector_undef:
	get_bad_stack
	bad_save_user_regs
	bl	rt_hw_trap_udef

	.align	5
vector_swi:
	get_bad_stack
	bad_save_user_regs
	bl 	rt_hw_trap_swi

	.align	5
vector_pabt:
	get_bad_stack
	bad_save_user_regs
	bl 	rt_hw_trap_pabt

	.align	5
vector_dabt:
	get_bad_stack
	bad_save_user_regs
	bl 	rt_hw_trap_dabt

	.align	5
vector_resv:
	get_bad_stack
	bad_save_user_regs
	bl 	rt_hw_trap_resv

.globl rt_interrupt_enter
.globl rt_interrupt_leave
.globl rt_thread_switch_interrput_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
vector_irq:
	stmfd	sp!, {r0-r12,lr}
	bl	rt_interrupt_enter
	bl	rt_hw_trap_irq
	bl	rt_interrupt_leave

	/* if rt_thread_switch_interrput_flag set, jump to _interrupt_thread_switch and don't return */
	ldr	r0, =rt_thread_switch_interrput_flag
	ldr	r1, [r0]
	cmp	r1, #1
	beq	_interrupt_thread_switch

	ldmfd	sp!, {r0-r12,lr}
	subs	pc, lr, #4

	.align	5
vector_fiq:
	stmfd	sp!,{r0-r7,lr}
	bl 	rt_hw_trap_fiq
	ldmfd	sp!,{r0-r7,lr}
	subs	pc,lr,#4


_interrupt_thread_switch:
	mov	r1,  #0				@ clear rt_thread_switch_interrput_flag
	str	r1,  [r0]

	ldmfd	sp!, {r0-r12,lr}@ reload saved registers
	stmfd	sp!, {r0-r3}	@ save r0-r3
	mov	r1,  sp
	add	sp,  sp, #16		@ restore sp
	sub	r2,  lr, #4			@ save old task pc to r2

	mrs	r3,  spsr			@ disable interrupt
	orr	r0,  r3, #NOINT
	msr	spsr_c, r0

	ldr	r0,  =.+8			@ switch to interrupted stack of task
	movs	pc,  r0

	stmfd	sp!, {r2}		@ push old task's pc
	stmfd	sp!, {r4-r12,lr}@ push old task's lr,r12-r4
	mov	r4,  r1				@ Special optimised code below
	mov	r5,  r3
	ldmfd	r4!, {r0-r3}
	stmfd	sp!, {r0-r3}	@ push old task's r3-r0
	stmfd	sp!, {r5}		@ push old task's psr
	mrs	r4,  spsr
	stmfd	sp!, {r4}		@ push old task's spsr

	ldr	r4,  =rt_interrupt_from_thread
	ldr	r5,  [r4]
	str	sp,  [r5]			@ store sp in preempted tasks's TCB

	ldr	r6,  =rt_interrupt_to_thread
	ldr	r6,  [r6]
	ldr	sp,  [r6]			@ get new task's stack pointer

	ldmfd	sp!, {r4}		@ pop new task's spsr
	msr	SPSR_cxsf, r4
	ldmfd	sp!, {r4}		@ pop new task's psr
	msr	CPSR_cxsf, r4

	ldmfd	sp!, {r0-r12,lr,pc}	@ pop new task's r0-r12,lr & pc

/*@}*/