dff8test.vbe

来自「i need of vhdl code for 32-bit risc proc」· VBE 代码 · 共 51 行

ENTITY dff8test IS
PORT (
Din : IN bit_vector(7 downto 0);
clk : IN BIT;
resetin : IN BIT;
enable : IN BIT;
selectbit : IN BIT;
Dout : OUT bit_vector(7 downto 0)
);
END dff8test;

ARCHITECTURE dff8test_arch OF dff8test IS

SIGNAL Reg : REG_VECTOR (7 downto 0) REGISTER;
SIGNAL int : bit_vector(7 downto 0);

BEGIN
flip_flop : BLOCK ( clk='0' AND NOT clk'STABLE AND enable='1' AND selectbit='1')


BEGIN
int(0) <= ( Din(0) AND (NOT(resetin)) );
int(1) <= ( Din(1) AND (NOT(resetin)) );
int(2) <= ( Din(2) AND (NOT(resetin)) );
int(3) <= ( Din(3) AND (NOT(resetin)) );
int(4) <= ( Din(4) AND (NOT(resetin)) );
int(5) <= ( Din(5) AND (NOT(resetin)) );
int(6) <= ( Din(6) AND (NOT(resetin)) );
int(7) <= ( Din(7) AND (NOT(resetin)) );

Reg(0) <= GUARDED int(0);
Reg(1) <= GUARDED int(1) ;
Reg(2) <= GUARDED int(2);
Reg(3) <= GUARDED int(3);
Reg(4) <= GUARDED int(4);
Reg(5) <= GUARDED int(5);
Reg(6) <= GUARDED int(6);
Reg(7) <= GUARDED int(7);

END BLOCK;

Dout(0) <= Reg(0);
Dout(1) <= Reg(1);
Dout(2) <= Reg(2);
Dout(3) <= Reg(3);
Dout(4) <= Reg(4);
Dout(5) <= Reg(5);
Dout(6) <= Reg(6);
Dout(7) <= Reg(7);

END;