add3.vbe

来自「i need of vhdl code for 32-bit risc proc」· VBE 代码 · 共 23 行

ENTITY add3 IS
PORT (
avala : IN bit_vector(2 downto 0);
bvala : IN bit_vector(2 downto 0);
resa : OUT bit_vector(2 downto 0);
carrouta : OUT BIT
);
END add3;

ARCHITECTURE add3_arch OF add3 IS

SIGNAL ca :bit_vector(1 downto 0);

begin
resa(0)<=avala(0) XOR bvala(0);
ca(0)<=avala(0) AND bvala(0);
resa(1)<=avala(1) XOR bvala(1) XOR  ca(0);
ca(1) <=( ( avala(1) AND bvala(1) ) OR  ( ( avala(1) XOR bvala(1) ) AND ca(0) ) );
resa(2) <=avala(2) XOR bvala(2) XOR ca(1);
carrouta <=( ( avala(2) AND bvala(2) ) OR  ( ( avala(2) XOR bvala(2) ) AND ca(1) ) );

end;