leftdecide.vbe

i need of vhdl code for 32-bit risc processor

ENTITY leftdecide IS
PORT(
valin: IN BIT_VECTOR(4 downto 0);
val1a: IN BIT_VECTOR(4 downto 0);
val2a: IN BIT_VECTOR(4 downto 0);
val3a: IN BIT_VECTOR(4 downto 0);
val4a: IN BIT_VECTOR(4 downto 0);
out1a : OUT BIT_VECTOR(4 downto 0);
expout : OUT BIT_VECTOR(2 downto 0 )
);
END leftdecide;

ARCHITECTURE leftdecide_arch OF leftdecide IS
begin
out1a(0) <= ( valin(4) AND valin(0) ) OR ( ( NOT(valin(4)) AND valin(3) ) AND val1a(0) ) OR  ( ( NOT(valin(4)) AND NOT(valin(3)) AND valin(2) ) AND val2a(0) ) OR  ( ( NOT(valin(4)) AND NOT(valin(3)) AND NOT(valin(2)) AND valin(1) ) AND val3a(0) ) OR ( ( NOT(valin(4)) AND NOT(valin(3)) AND NOT(valin(2)) AND NOT(valin(1)) AND valin(0) ) AND val4a(0) ) ; 
  
out1a(1) <= ( valin(4) AND valin(1) ) OR ( ( NOT(valin(4)) AND valin(3) ) AND val1a(1) ) OR  ( ( NOT(valin(4)) AND NOT(valin(3)) AND valin(2) ) AND val2a(1) ) OR  ( ( NOT(valin(4)) AND NOT(valin(3)) AND NOT(valin(2)) AND valin(1) ) AND val3a(1) ) OR ( ( NOT(valin(4)) AND NOT(valin(3)) AND NOT(valin(2)) AND NOT(valin(1)) AND valin(0) ) AND val4a(1) ) ;

out1a(2) <= ( valin(4) AND valin(2) ) OR ( ( NOT(valin(4)) AND valin(3) ) AND val1a(2) ) OR  ( ( NOT(valin(4)) AND NOT(valin(3)) AND valin(2) ) AND val2a(2) ) OR  ( ( NOT(valin(4)) AND NOT(valin(3)) AND NOT(valin(2)) AND valin(1) ) AND val3a(2) ) OR ( ( NOT(valin(4)) AND NOT(valin(3)) AND NOT(valin(2)) AND NOT(valin(1)) AND valin(0) ) AND val4a(2) ) ;

out1a(3) <= ( valin(4) AND valin(3) ) OR ( ( NOT(valin(4)) AND valin(3) ) AND val1a(3) ) OR  ( ( NOT(valin(4)) AND NOT(valin(3)) AND valin(2) ) AND val2a(3) ) OR  ( ( NOT(valin(4)) AND NOT(valin(3)) AND NOT(valin(2)) AND valin(1) ) AND val3a(3) ) OR ( ( NOT(valin(4)) AND NOT(valin(3)) AND NOT(valin(2)) AND NOT(valin(1)) AND valin(0) ) AND val4a(3) ) ;

out1a(4) <= ( valin(4) AND valin(4) ) OR ( ( NOT(valin(4)) AND valin(3) ) AND val1a(4) ) OR  ( ( NOT(valin(4)) AND NOT(valin(3)) AND valin(2) ) AND val2a(4) ) OR  ( ( NOT(valin(4)) AND NOT(valin(3)) AND NOT(valin(2)) AND valin(1) ) AND val3a(4) ) OR ( ( NOT(valin(4)) AND NOT(valin(3)) AND NOT(valin(2)) AND NOT(valin(1)) AND valin(0) ) AND val4a(4) ) ;


expout(2) <= ( NOT(valin(4)) AND NOT(valin(3)) AND NOT(valin(2)) AND NOT(valin(1)) AND valin(0) );
expout(1) <= ( NOT(valin(4)) AND NOT(valin(3)) AND NOT(valin(2)) AND valin(1) ) OR ( NOT(valin(4)) AND NOT(valin(3)) AND valin(2) );
expout(0) <= ( NOT(valin(4)) AND valin(3) ) OR ( NOT(valin(4)) AND NOT(valin(3)) AND NOT(valin(2)) AND valin(1) ) ;
end;