rol8.vbe

i need of vhdl code for 32-bit risc processor

ENTITY rol8 IS
PORT (
rl1 : IN bit_vector(7 downto 0);
rl2 : IN bit_vector(7 downto 0);
rout : OUT bit_vector(7 downto 0)
);
END rol8;

ARCHITECTURE rol8_arch OF rol8 IS

BEGIN
  rout(7)<=(( rl1(7) AND ( NOT(rl2(2)) ) AND ( NOT(rl2(1)) ) AND ( NOT(rl2(0))) )OR
           ( rl1(0) AND ( NOT(rl2(2)) ) AND ( NOT(rl2(1)) ) AND  rl2(0) ) OR
           ( rl1(1) AND ( NOT(rl2(2)) ) AND rl2(1) AND ( NOT(rl2(0)) ) )OR
           ( rl1(2) AND ( NOT(rl2(2)) ) AND rl2(1) AND rl2(0) ) OR
           ( rl1(3) AND rl2(2) AND ( NOT(rl2(1)) ) AND ( NOT(rl2(0))) ) OR
           ( rl1(4) AND rl2(2) AND ( NOT(rl2(1)) ) AND rl2(0) ) OR
           ( rl1(5) AND rl2(2) AND rl2(1) AND ( NOT(rl2(0))) ) OR
           ( rl1(6) AND rl2(2) AND rl2(1) AND  rl2(0) )); 
  
  rout(6)<=( rl1(6) AND (NOT(rl2(2))) AND (NOT(rl2(1))) AND (NOT(rl2(0))) )OR
           ( rl1(7) AND (NOT(rl2(2))) AND (NOT(rl2(1))) AND  rl2(0) ) OR
           ( rl1(0) AND (NOT(rl2(2))) AND rl2(1) AND (NOT(rl2(0))) )OR
           ( rl1(1) AND (NOT(rl2(2))) AND rl2(1) AND rl2(0) ) OR
           ( rl1(2) AND rl2(2) AND (NOT(rl2(1))) AND (NOT(rl2(0))) ) OR
           ( rl1(3) AND rl2(2) AND (NOT(rl2(1))) AND rl2(0) ) OR
           ( rl1(4) AND rl2(2) AND rl2(1) AND (NOT(rl2(0))) ) OR
           ( rl1(5) AND rl2(2) AND rl2(1) AND  rl2(0) ); 
  
  rout(5)<=( rl1(5) AND (NOT(rl2(2))) AND (NOT(rl2(1))) AND (NOT(rl2(0))) )OR
           ( rl1(6) AND (NOT(rl2(2))) AND (NOT(rl2(1))) AND  rl2(0) ) OR
           ( rl1(7) AND (NOT(rl2(2))) AND rl2(1) AND (NOT(rl2(0))) ) OR
           ( rl1(0) AND (NOT(rl2(2))) AND rl2(1) AND rl2(0) ) OR
           ( rl1(1) AND rl2(2) AND (NOT(rl2(1))) AND (NOT(rl2(0))) ) OR
           ( rl1(2) AND rl2(2) AND (NOT(rl2(1))) AND rl2(0) ) OR
           ( rl1(3) AND rl2(2) AND rl2(1) AND (NOT(rl2(0))) ) OR
           ( rl1(4) AND rl2(2) AND rl2(1) AND  rl2(0) ); 
           
  rout(4)<=( rl1(4) AND (NOT(rl2(2))) AND (NOT(rl2(1))) AND (NOT(rl2(0))) )OR
           ( rl1(5) AND (NOT(rl2(2))) AND (NOT(rl2(1))) AND  rl2(0) ) OR
           ( rl1(6) AND (NOT(rl2(2))) AND rl2(1) AND (NOT(rl2(0))) )OR
           ( rl1(7) AND (NOT(rl2(2))) AND rl2(1) AND rl2(0) ) OR
           ( rl1(0) AND rl2(2) AND (NOT(rl2(1))) AND (NOT(rl2(0))) ) OR
           ( rl1(1) AND rl2(2) AND (NOT(rl2(1))) AND rl2(0) ) OR
           ( rl1(2) AND rl2(2) AND rl2(1) AND (NOT(rl2(0))) ) OR
           ( rl1(3) AND rl2(2) AND rl2(1) AND  rl2(0) ); 
           
  rout(3)<=( rl1(3) AND (NOT(rl2(2))) AND (NOT(rl2(1))) AND (NOT(rl2(0))) )OR
           ( rl1(4) AND (NOT(rl2(2))) AND (NOT(rl2(1))) AND  rl2(0) ) OR
           ( rl1(5) AND (NOT(rl2(2))) AND rl2(1) AND (NOT(rl2(0))) )OR
           ( rl1(6) AND (NOT(rl2(2))) AND rl2(1) AND  rl2(0) ) OR
           ( rl1(7) AND rl2(2) AND (NOT(rl2(1))) AND (NOT(rl2(0))) ) OR
           ( rl1(0) AND rl2(2) AND (NOT(rl2(1))) AND rl2(0) ) OR
           ( rl1(1) AND rl2(2) AND rl2(1) AND (NOT(rl2(0))) ) OR
           ( rl1(2) AND rl2(2) AND rl2(1) AND  rl2(0) ); 
           
  rout(2)<=( rl1(2) AND (NOT(rl2(2))) AND (NOT(rl2(1))) AND (NOT(rl2(0))) )OR
           ( rl1(3) AND (NOT(rl2(2))) AND (NOT(rl2(1))) AND  rl2(0) ) OR
           ( rl1(4) AND (NOT(rl2(2))) AND rl2(1) AND (NOT(rl2(0))) )OR
           ( rl1(5) AND (NOT(rl2(2))) AND rl2(1) AND rl2(0) ) OR
           ( rl1(6) AND rl2(2) AND (NOT(rl2(1))) AND (NOT(rl2(0))) ) OR
           ( rl1(7) AND rl2(2) AND (NOT(rl2(1))) AND rl2(0) ) OR
           ( rl1(0) AND rl2(2) AND rl2(1) AND (NOT(rl2(0))) ) OR
           ( rl1(1) AND rl2(2) AND rl2(1) AND  rl2(0) );
           
  rout(1)<=( rl1(1) AND (NOT(rl2(2))) AND (NOT(rl2(1))) AND (NOT(rl2(0))) )OR
           ( rl1(2) AND (NOT(rl2(2))) AND (NOT(rl2(1))) AND  rl2(0) ) OR
           ( rl1(3) AND (NOT(rl2(2))) AND rl2(1) AND (NOT(rl2(0)))) OR
           ( rl1(4) AND (NOT(rl2(2))) AND rl2(1) AND rl2(0) ) OR
           ( rl1(5) AND rl2(2) AND (NOT(rl2(1))) AND (NOT(rl2(0))) ) OR
           ( rl1(6) AND rl2(2) AND (NOT(rl2(1))) AND rl2(0) ) OR
           ( rl1(7) AND rl2(2) AND rl2(1) AND (NOT(rl2(0))) ) OR
           ( rl1(0) AND rl2(2) AND rl2(1) AND  rl2(0) );
           
  rout(0)<=( rl1(0) AND (NOT(rl2(2))) AND (NOT(rl2(1))) AND (NOT(rl2(0))) )OR
           ( rl1(1) AND (NOT(rl2(2))) AND (NOT(rl2(1))) AND  rl2(0) ) OR
           ( rl1(2) AND (NOT(rl2(2))) AND rl2(1) AND (NOT(rl2(0)))) OR
           ( rl1(3) AND (NOT(rl2(2))) AND rl2(1) AND rl2(0) ) OR
           ( rl1(4) AND rl2(2) AND (NOT(rl2(1))) AND (NOT(rl2(0))) ) OR
           ( rl1(5) AND rl2(2) AND (NOT(rl2(1))) AND rl2(0) ) OR
           ( rl1(6) AND rl2(2) AND rl2(1) AND (NOT(rl2(0))) ) OR
           ( rl1(7) AND rl2(2) AND rl2(1) AND  rl2(0) );
           
END;