aluearlier_1.vst

i need of vhdl code for 32-bit risc processor

ENTITY alu IS
PORT (
al1: IN bit_vector(7 downto 0);
al2: IN bit_vector(7 downto 0);
sel : IN bit_vector(2 downto 0);
alout : OUT bit_vector(7 downto 0)
);
END alu ;

ARCHITECTURE alu_arch OF alu IS

COMPONENT cla
PORT (
a : IN bit_vector(7 downto 0);
b : IN bit_vector(7 downto 0);
c0 : IN BIT;
s : OUT bit_vector(7 downto 0);
cout : OUT BIT
);
END COMPONENT ;

COMPONENT rol8
PORT (
rl1 : IN bit_vector(7 downto 0);
rl2 : IN bit_vector(7 downto 0);
rout : OUT bit_vector(7 downto 0)
);
END COMPONENT ;

COMPONENT xor8 
PORT (
xn1 : IN bit_vector(7 downto 0);
xn2 : IN bit_vector(7 downto 0);
xout : OUT bit_vector(7 downto 0)
);
END COMPONENT;

COMPONENT sub8
PORT (
sn1 : IN bit_vector(7 downto 0);
sn2 : IN bit_vector(7 downto 0);
sout : OUT bit_vector(7 downto 0)
);
END COMPONENT;

COMPONENT and8
PORT (
an1 : IN bit_vector(7 downto 0);
an2 : IN bit_vector(7 downto 0);
aout : OUT bit_vector(7 downto 0)
);
END COMPONENT;

COMPONENT or8
PORT (
on1 : IN bit_vector(7 downto 0);
on2 : IN bit_vector(7 downto 0);
oout : OUT bit_vector(7 downto 0)
);
END COMPONENT;

COMPONENT fwd 
PORT (
inpu1 : IN bit_vector(7 downto 0);
inpu2 : IN bit_vector(7 downto 0);
outpu : OUT bit_vector(7 downto 0)
);
END COMPONENT;

COMPONENT buffer0
PORT (
bo1 : IN BIT;
bo2 : OUT BIT
);
END COMPONENT;

COMPONENT newmux8to1
PORT (
inn1 : IN BIT;
inn2 : IN BIT;
inn3 : IN BIT;
inn4 : IN BIT;
inn5 : IN BIT;
inn6 : IN BIT;
inn7 : IN BIT;
inn8 : IN BIT;
enn1 : IN BIT;
enn2 : IN BIT;
enn3 : IN BIT;
outn1 : OUT BIT
);
END COMPONENT;

SIGNAL addout : BIT_VECTOR(7 downto 0);
SIGNAL subout : BIT_VECTOR(7 downto 0);
SIGNAL rolout : BIT_VECTOR(7 downto 0);
SIGNAL xorout : BIT_VECTOR(7 downto 0);
SIGNAL andout : BIT_VECTOR(7 downto 0);
SIGNAL orout : BIT_VECTOR(7 downto 0);
SIGNAL fwdout : BIT_VECTOR(7 downto 0);
SIGNAL c1add : BIT;
SIGNAL c2add : BIT;

BEGIN

buffer0 : buffer0 PORT MAP(al1(0),c1add);

adder : cla PORT MAP(al1,al2,c1add,addout,c2add);

subtr : sub8 PORT MAP(al1,al2,subout);

rol : rol8 PORT MAP(al1,al2,rolout);

xorfn : xor8 PORT MAP(al1,al2,xorout);

andfn : and8 PORT MAP(al1,al2,andout);

orfn : or8 PORT MAP(al1,al2,orout);

fwd : fwd PORT MAP(al1,al2,fwdout);

mux1 : newmux8to1 PORT MAP(addout(0),subout(0),rolout(0),xorout(0),andout(0),orout(0),c1add,fwdout(0),sel(2),sel(1),sel(0),alout(0));
mux2 : newmux8to1 PORT MAP(addout(1),subout(1),rolout(1),xorout(1),andout(1),orout(1),c1add,fwdout(1),sel(2),sel(1),sel(0),alout(1));
mux3 : newmux8to1 PORT MAP(addout(2),subout(2),rolout(2),xorout(2),andout(2),orout(2),c1add,fwdout(2),sel(2),sel(1),sel(0),alout(2));
mux4 : newmux8to1 PORT MAP(addout(3),subout(3),rolout(3),xorout(3),andout(3),orout(3),c1add,fwdout(3),sel(2),sel(1),sel(0),alout(3));
mux5 : newmux8to1 PORT MAP(addout(4),subout(4),rolout(4),xorout(4),andout(4),orout(4),c1add,fwdout(4),sel(2),sel(1),sel(0),alout(4));
mux6 : newmux8to1 PORT MAP(addout(5),subout(5),rolout(5),xorout(5),andout(5),orout(5),c1add,fwdout(5),sel(2),sel(1),sel(0),alout(5));
mux7 : newmux8to1 PORT MAP(addout(6),subout(6),rolout(6),xorout(6),andout(6),orout(6),c1add,fwdout(6),sel(2),sel(1),sel(0),alout(6));
mux8 : newmux8to1 PORT MAP(addout(7),subout(7),rolout(7),xorout(7),andout(7),orout(7),c1add,fwdout(7),sel(2),sel(1),sel(0),alout(7));

END;