regfile.vst

i need of vhdl code for 32-bit risc processor

ENTITY regfile IS
PORT (
aadr: IN bit_vector(2 downto 0);
badr: IN bit_vector(2 downto 0);
wadr: IN bit_vector(2 downto 0);
wdata: IN bit_vector(7 downto 0);
wenable: IN BIT;
clock : IN BIT;
resetreg : IN BIT;
a : OUT bit_vector(7 downto 0);
b : OUT bit_vector(7 downto 0)
);
END regfile;

ARCHITECTURE regfile_arch OF regfile IS

COMPONENT decoder3to8
PORT (
input : IN bit_vector ( 2 downto 0 );
output : OUT bit_vector ( 7 downto 0 )
);
END COMPONENT ;

COMPONENT dff8test
PORT (
Din : IN bit_vector(7 downto 0);
clk : IN BIT;
resetin : IN BIT;
enable : IN BIT;
selectbit : IN BIT;
Dout : OUT bit_vector(7 downto 0)
);
END COMPONENT ;

COMPONENT newmux8to1
PORT (
inn1 : IN BIT;
inn2 : IN BIT;
inn3 : IN BIT;
inn4 : IN BIT;
inn5 : IN BIT;
inn6 : IN BIT;
inn7 : IN BIT;
inn8 : IN BIT;
enn1 : IN BIT;
enn2 : IN BIT;
enn3 : IN BIT;
outn1 : OUT BIT
);
END COMPONENT ;

COMPONENT orgate 
PORT (
a3 : IN BIT;
b3 : IN BIT;
c3 : OUT BIT 
);
END COMPONENT;

SIGNAL wdecoder : BIT_VECTOR(7 downto 0);
SIGNAL wdecoderres : BIT_VECTOR(7 downto 0);
SIGNAL d1 : BIT_VECTOR(7 downto 0);
SIGNAL d2 : BIT_VECTOR(7 downto 0);
SIGNAL d3 : BIT_VECTOR(7 downto 0);
SIGNAL d4 : BIT_VECTOR(7 downto 0);
SIGNAL d5 : BIT_VECTOR(7 downto 0);
SIGNAL d6 : BIT_VECTOR(7 downto 0);
SIGNAL d7 : BIT_VECTOR(7 downto 0);
SIGNAL d8 : BIT_VECTOR(7 downto 0);
SIGNAL wen : BIT;

BEGIN

decoder3to8_1 : decoder3to8 PORT MAP(wadr,wdecoderres);


--to adjust value wen during reset
orgate : orgate PORT MAP(wenable,resetreg,wen);

--to adjust value wdecoder during reset
orgate1 : orgate PORT MAP(wdecoderres(0),resetreg,wdecoder(0));
orgate2 : orgate PORT MAP(wdecoderres(1),resetreg,wdecoder(1));
orgate3 : orgate PORT MAP(wdecoderres(2),resetreg,wdecoder(2));
orgate4 : orgate PORT MAP(wdecoderres(3),resetreg,wdecoder(3));
orgate5 : orgate PORT MAP(wdecoderres(4),resetreg,wdecoder(4));
orgate6 : orgate PORT MAP(wdecoderres(5),resetreg,wdecoder(5));
orgate7 : orgate PORT MAP(wdecoderres(6),resetreg,wdecoder(6));
orgate8 : orgate PORT MAP(wdecoderres(7),resetreg,wdecoder(7));

dff8_0 : dff8test PORT MAP(wdata,clock,resetreg,wen,wdecoder(0),d1);
dff8_1 : dff8test PORT MAP(wdata,clock,resetreg,wen,wdecoder(1),d2);
dff8_2 : dff8test PORT MAP(wdata,clock,resetreg,wen,wdecoder(2),d3);
dff8_3 : dff8test PORT MAP(wdata,clock,resetreg,wen,wdecoder(3),d4);
dff8_4 : dff8test PORT MAP(wdata,clock,resetreg,wen,wdecoder(4),d5);
dff8_5 : dff8test PORT MAP(wdata,clock,resetreg,wen,wdecoder(5),d6);
dff8_6 : dff8test PORT MAP(wdata,clock,resetreg,wen,wdecoder(6),d7);
dff8_7 : dff8test PORT MAP(wdata,clock,resetreg,wen,wdecoder(7),d8);

muxa1 : newmux8to1 PORT MAP(d1(0),d2(0),d3(0),d4(0),d5(0),d6(0),d7(0),d8(0),aadr(2),aadr(1),aadr(0),a(0));
muxa2 : newmux8to1 PORT MAP(d1(1),d2(1),d3(1),d4(1),d5(1),d6(1),d7(1),d8(1),aadr(2),aadr(1),aadr(0),a(1));
muxa3 : newmux8to1 PORT MAP(d1(2),d2(2),d3(2),d4(2),d5(2),d6(2),d7(2),d8(2),aadr(2),aadr(1),aadr(0),a(2));
muxa4 : newmux8to1 PORT MAP(d1(3),d2(3),d3(3),d4(3),d5(3),d6(3),d7(3),d8(3),aadr(2),aadr(1),aadr(0),a(3));
muxa5 : newmux8to1 PORT MAP(d1(4),d2(4),d3(4),d4(4),d5(4),d6(4),d7(4),d8(4),aadr(2),aadr(1),aadr(0),a(4));
muxa6 : newmux8to1 PORT MAP(d1(5),d2(5),d3(5),d4(5),d5(5),d6(5),d7(5),d8(5),aadr(2),aadr(1),aadr(0),a(5));
muxa7 : newmux8to1 PORT MAP(d1(6),d2(6),d3(6),d4(6),d5(6),d6(6),d7(6),d8(6),aadr(2),aadr(1),aadr(0),a(6));
muxa8 : newmux8to1 PORT MAP(d1(7),d2(7),d3(7),d4(7),d5(7),d6(7),d7(7),d8(7),aadr(2),aadr(1),aadr(0),a(7));


muxb1 : newmux8to1 PORT MAP(d1(0),d2(0),d3(0),d4(0),d5(0),d6(0),d7(0),d8(0),badr(2),badr(1),badr(0),b(0));
muxb2 : newmux8to1 PORT MAP(d1(1),d2(1),d3(1),d4(1),d5(1),d6(1),d7(1),d8(1),badr(2),badr(1),badr(0),b(1));
muxb3 : newmux8to1 PORT MAP(d1(2),d2(2),d3(2),d4(2),d5(2),d6(2),d7(2),d8(2),badr(2),badr(1),badr(0),b(2));
muxb4 : newmux8to1 PORT MAP(d1(3),d2(3),d3(3),d4(3),d5(3),d6(3),d7(3),d8(3),badr(2),badr(1),badr(0),b(3));
muxb5 : newmux8to1 PORT MAP(d1(4),d2(4),d3(4),d4(4),d5(4),d6(4),d7(4),d8(4),badr(2),badr(1),badr(0),b(4));
muxb6 : newmux8to1 PORT MAP(d1(5),d2(5),d3(5),d4(5),d5(5),d6(5),d7(5),d8(5),badr(2),badr(1),badr(0),b(5));
muxb7 : newmux8to1 PORT MAP(d1(6),d2(6),d3(6),d4(6),d5(6),d6(6),d7(6),d8(6),badr(2),badr(1),badr(0),b(6));
muxb8 : newmux8to1 PORT MAP(d1(7),d2(7),d3(7),d4(7),d5(7),d6(7),d7(7),d8(7),badr(2),badr(1),badr(0),b(7));



END;