sub3.vst

来自「i need of vhdl code for 32-bit risc proc」· VST 代码 · 共 54 行

ENTITY sub3 IS
PORT (
av : IN bit_vector(2 downto 0);
bv : IN bit_vector(2 downto 0);
re : OUT bit_vector(2 downto 0);
car : OUT BIT
);
END sub3;

ARCHITECTURE sub3_arch OF sub3 IS

COMPONENT add3 
PORT (
avala : IN bit_vector(2 downto 0);
bvala : IN bit_vector(2 downto 0);
resa : OUT bit_vector(2 downto 0);
carrouta : OUT BIT
);
END COMPONENT;

COMPONENT not3 
PORT (
n1 : IN bit_vector(2 downto 0);
n2 : OUT bit_vector(2 downto 0)
);
END COMPONENT;

COMPONENT out13
PORT (
anyin : In BIT;
oup : OUT bit_vector(2 downto 0)
);
END COMPONENT;


SIGNAL bv1 : BIT_VECTOR(2 downto 0);
SIGNAL sum1 : BIT_VECTOR(2 downto 0);
SIGNAL sub1 : BIT_VECTOR(2 downto 0);
--SIGNAL bv2 : BIT_VECTOR(2 downto 0);
SIGNAL c1 : BIT;
--SIGNAL c2 : BIT;

BEGIN

not1 : not3 PORT MAP(bv,bv1);

out13 : out13 PORT MAP(bv(0),sub1);

add3a : add3 PORT MAP(sub1,bv1,sum1,c1);

add3b : add3 PORT MAP(av,sum1,re,car);

end;