swapres.vbe

i need of vhdl code for 32-bit risc processor

ENTITY swapres IS
PORT(
op1 : IN BIT_VECTOR(7 downto 0);
op2 : IN BIT_VECTOR(7 downto 0);
decidebit : IN BIT;
out1 : OUT BIT_VECTOR(7 downto 0);
out2 : OUT BIT_VECTOR(7 downto 0)
);
END swapres;

ARCHITECTURE swapres_arch OF swapres IS

BEGIN

out1(0) <= ( (op1(0) AND NOT(decidebit) ) OR ( op2(0) AND decidebit ) );
out1(1) <= ( (op1(1) AND NOT(decidebit) ) OR ( op2(1) AND decidebit ) );
out1(2) <= ( (op1(2) AND NOT(decidebit) ) OR ( op2(2) AND decidebit ) );
out1(3) <= ( (op1(3) AND NOT(decidebit) ) OR ( op2(3) AND decidebit ) );
out1(4) <= ( (op1(4) AND NOT(decidebit) ) OR ( op2(4) AND decidebit ) );
out1(5) <= ( (op1(5) AND NOT(decidebit) ) OR ( op2(5) AND decidebit ) );
out1(6) <= ( (op1(6) AND NOT(decidebit) ) OR ( op2(6) AND decidebit ) );
out1(7) <= ( (op1(7) AND NOT(decidebit) ) OR ( op2(7) AND decidebit ) );

out2(0) <= ( (op2(0) AND NOT(decidebit) ) OR ( op1(0) AND decidebit ) );
out2(1) <= ( (op2(1) AND NOT(decidebit) ) OR ( op1(1) AND decidebit ) );
out2(2) <= ( (op2(2) AND NOT(decidebit) ) OR ( op1(2) AND decidebit ) );
out2(3) <= ( (op2(3) AND NOT(decidebit) ) OR ( op1(3) AND decidebit ) );
out2(4) <= ( (op2(4) AND NOT(decidebit) ) OR ( op1(4) AND decidebit ) );
out2(5) <= ( (op2(5) AND NOT(decidebit) ) OR ( op1(5) AND decidebit ) );
out2(6) <= ( (op2(6) AND NOT(decidebit) ) OR ( op1(6) AND decidebit ) );
out2(7) <= ( (op2(7) AND NOT(decidebit) ) OR ( op1(7) AND decidebit ) );
end;