writeback.vst

i need of vhdl code for 32-bit risc processor

ENTITY writeback IS
PORT (
insir5out : IN bit_vector(15 downto 0);
alucalval : IN bit_vector(7 downto 0); 
memoutdata : IN bit_vector(7 downto 0);
clock5 : IN BIT;
reset5 : IN BIT;
writebackval : OUT bit_vector(7 downto 0);
writebackreg : OUT bit_vector(2 downto 0);
writebackena : OUT BIT
);
END writeback;

ARCHITECTURE writeback_arch OF writeback IS

COMPONENT instreg 
PORT (
Din1 : IN bit_vector(15 downto 0);
clk1 : IN BIT;
enable1 : IN BIT;
resetir : IN BIT;
Dout1 : OUT bit_vector(15 downto 0)
);
END COMPONENT ;


COMPONENT pc
PORT (
Din2 : IN bit_vector(7 downto 0);
clk2 : IN BIT;
enable2 : IN BIT;
resetpc : IN BIT;
Dout2 : OUT bit_vector(7 downto 0)
);
END COMPONENT ;

COMPONENT mux2to1
PORT (
inp1 : IN BIT;
inp2 : IN BIT;
en : IN BIT;
outp : OUT BIT
);
END COMPONENT;

COMPONENT andgate 
PORT (
a2 : IN BIT;
b2 : IN BIT;
c2 : OUT BIT 
);
END COMPONENT;

COMPONENT orgate 
PORT (
a3 : IN BIT;
b3 : IN BIT;
c3 : OUT BIT 
);
END COMPONENT;

COMPONENT notgate
PORT (
a4 : IN BIT;
c4 : OUT BIT
);
END COMPONENT;

COMPONENT bitconv 
PORT (
bit1 : IN BIT;
bit2 : IN BIT;
bit3 : IN BIT;
outvec : OUT bit_vector(2 downto 0)
);
END COMPONENT;

COMPONENT wbreg 
PORT (
Din5 : IN bit_vector(2 downto 0);
clk5 : IN BIT;
enable5 : IN BIT;
resetv : IN BIT;
Dout5 : OUT bit_vector(2 downto 0)
);
END COMPONENT;


COMPONENT bitreg 
PORT (
bitin : IN BIT;
clk3 : IN BIT;
enable3 : IN BIT;
resetin : IN BIT;
bitout : OUT BIT
);
END COMPONENT;

COMPONENT regwren 
PORT (
inputval : IN BIT_VECTOR(15 downto 0);
outputval: OUT BIT
);
END COMPONENT;

COMPONENT buffer1 
PORT (
bu1 : IN BIT;
bu2 : OUT BIT
);
END COMPONENT;

SIGNAL onesig5 : BIT;
--SIGNAL orres1 : BIT;
--SIGNAL notres12 : BIT;
--SIGNAL notres13 : BIT;
SIGNAL notres15 : BIT;
SIGNAL notres11 : BIT;
SIGNAL andresa : BIT;
SIGNAL andresb : BIT;
SIGNAL andrese : BIT;
--SIGNAL andresf : BIT;
--SIGNAL andresg : BIT;
--SIGNAL andres1 : BIT;
--SIGNAL andres2 : BIT;
SIGNAL writebackenatemp : BIT;
--SIGNAL mux5out : BIT_VECTOR(7 downto 0);
SIGNAL writebackregtemp : BIT_VECTOR(2 downto 0);
SIGNAL writebackvalt : BIT_VECTOR(7 downto 0);


BEGIN

--selecting value for mux out
not5_a15 : notgate PORT MAP(insir5out(15),notres15);
not5_a11 : notgate PORT MAP(insir5out(11),notres11);
andab : andgate PORT MAP(notres11,notres15,andresa);
andac : andgate PORT MAP(insir5out(12),insir5out(13),andresb);
andad : andgate PORT MAP(andresa,andresb,andrese);


mux2to1_5a : mux2to1 PORT MAP(alucalval(0),memoutdata(0),andrese,writebackvalt(0));
mux2to1_5b : mux2to1 PORT MAP(alucalval(1),memoutdata(1),andrese,writebackvalt(1));
mux2to1_5c : mux2to1 PORT MAP(alucalval(2),memoutdata(2),andrese,writebackvalt(2));
mux2to1_5d : mux2to1 PORT MAP(alucalval(3),memoutdata(3),andrese,writebackvalt(3));
mux2to1_5f : mux2to1 PORT MAP(alucalval(4),memoutdata(4),andrese,writebackvalt(4));
mux2to1_5g : mux2to1 PORT MAP(alucalval(5),memoutdata(5),andrese,writebackvalt(5));
mux2to1_5h : mux2to1 PORT MAP(alucalval(6),memoutdata(6),andrese,writebackvalt(6));
mux2to1_5i : mux2to1 PORT MAP(alucalval(7),memoutdata(7),andrese,writebackvalt(7));

writebackval : pc PORT MAP(writebackvalt,clock5,onesig5,reset5,writebackval); 

buffer1_5 : buffer1 PORT MAP(clock5,onesig5);

bitconv5 : bitconv PORT MAP(insir5out(6),insir5out(7),insir5out(8),writebackregtemp);

wbregtemp : wbreg PORT MAP(writebackregtemp,clock5,onesig5,reset5,writebackreg);



--to Write back enable calculation
--not5_12 : notgate PORT MAP(insir5out(12),notres12);
--not5_13 : notgate PORT MAP(insir5out(13),notres13);
--use sigs 11 and 15 of mux selecftion
--andab1 : andgate PORT MAP(notres13,insir5out(12),andresf);
--andad1 : andgate PORT MAP(andresa,andresf,andres2);

--andab2 : andgate PORT MAP(notres12,insir5out(13),andresg);
--or5 : orgate PORT MAP(andresg,insir5out(14),orres1);
--andd2 : andgate PORT MAP(orres1,insir5out(15),andres1);

--or5_1 : orgate port map(andres1,andres2,writebackenatemp );

regwren : regwren PORT MAP(insir5out,writebackenatemp);

bitreg : bitreg PORT MAP(writebackenatemp,clock5,onesig5,reset5,writebackena);

end;