instreg.vbe

i need of vhdl code for 32-bit risc processor

-- Instruction register component
ENTITY instreg IS
PORT (
Din1 : IN bit_vector(15 downto 0);
clk1 : IN BIT;
enable1 : IN BIT;
resetir : IN BIT;
Dout1 : OUT bit_vector(15 downto 0)
);
END instreg;

ARCHITECTURE instreg_arch OF instreg IS

SIGNAL Reg1 : REG_VECTOR (15 downto 0) REGISTER;

BEGIN

flip_flop : BLOCK ( clk1='1' AND NOT clk1'STABLE AND enable1='1') 

BEGIN
Reg1(0) <= GUARDED ( Din1(0) AND (NOT(resetir)) );
Reg1(1) <= GUARDED ( Din1(1) AND (NOT(resetir)) );
Reg1(2) <= GUARDED ( Din1(2) AND (NOT(resetir)) );
Reg1(3) <= GUARDED ( Din1(3) AND (NOT(resetir)) );
Reg1(4) <= GUARDED ( Din1(4) AND (NOT(resetir)) );
Reg1(5) <= GUARDED ( Din1(5) AND (NOT(resetir)) );
Reg1(6) <= GUARDED ( Din1(6) AND (NOT(resetir)) );
Reg1(7) <= GUARDED ( Din1(7) AND (NOT(resetir)) );
Reg1(8) <= GUARDED ( Din1(8) AND (NOT(resetir)) );
Reg1(9) <= GUARDED ( Din1(9) AND (NOT(resetir)) );
Reg1(10) <= GUARDED ( Din1(10) AND (NOT(resetir)) );
Reg1(11) <= GUARDED ( Din1(11) AND (NOT(resetir)) );
Reg1(12) <= GUARDED ( Din1(12) AND (NOT(resetir)) );
Reg1(13) <= GUARDED ( Din1(13) AND (NOT(resetir)) );
Reg1(14) <= GUARDED ( Din1(14) AND (NOT(resetir)) );
Reg1(15) <= GUARDED ( Din1(15) AND (NOT(resetir)) );
END BLOCK;

Dout1(0) <= Reg1(0);
Dout1(1) <= Reg1(1);
Dout1(2) <= Reg1(2);
Dout1(3) <= Reg1(3);
Dout1(4) <= Reg1(4);
Dout1(5) <= Reg1(5);
Dout1(6) <= Reg1(6);
Dout1(7) <= Reg1(7);
Dout1(8) <= Reg1(8);
Dout1(9) <= Reg1(9);
Dout1(10) <= Reg1(10);
Dout1(11) <= Reg1(11);
Dout1(12) <= Reg1(12);
Dout1(13) <= Reg1(13);
Dout1(14) <= Reg1(14);
Dout1(15) <= Reg1(15);


END;