processor.vst

i need of vhdl code for 32-bit risc processor

ENTITY processor IS
PORT (
clock : IN BIT;
instruction : IN bit_vector(15 downto 0);
readdata : IN bit_vector(7 downto 0);
reset: IN BIT;
instadd : OUT bit_vector(7 downto 0);
memorywriteenable : OUT BIT;
memaddr : OUT bit_vector(7 downto 0);
writedata : OUT bit_vector(7 downto 0)
);
END processor;


ARCHITECTURE processor_arch OF processor IS

COMPONENT instfetch 
PORT (
aluout : IN bit_vector(7 downto 0);
instinp : IN bit_vector(15 downto 0);
branch : IN BIT;
reset1 : IN BIT;
clock1 : IN BIT;
irout : OUT bit_vector(15 downto 0);
pcout : OUT bit_vector(7 downto 0)
);
END COMPONENT;


COMPONENT instdecode 
PORT (
prcnt2out : IN bit_vector(7 downto 0);
insir2out : IN bit_vector(15 downto 0);
clock2 : IN BIT;
writeadd : IN bit_vector(2 downto 0);
writedata : IN bit_vector(7 downto 0);
writeen : IN BIT;
reset2 : IN BIT;
branchcond : OUT BIT;
ir3out : OUT bit_vector(15 downto 0);
a3out : OUT bit_vector(7 downto 0);
b3out : OUT bit_vector(7 downto 0);
imout : OUT bit_vector(7 downto 0);
newbranch : out bit_vector(7 downto 0)
);
END COMPONENT;


COMPONENT instexec 
PORT (
insir3out : IN bit_vector(15 downto 0);
a3outinp : IN bit_vector(7 downto 0);
b3outinp : IN bit_vector(7 downto 0);
imoutinp : IN bit_vector(7 downto 0);
clock3 : IN BIT;
reset3 : IN BIT;
b3regout : OUT bit_vector(7 downto 0);
ir4out : OUT bit_vector(15 downto 0);
aluregout : OUT bit_vector(7 downto 0) 
);
END COMPONENT;


COMPONENT memaccess 
PORT (
insir4out : IN bit_vector(15 downto 0);
datafake : IN bit_vector(7 downto 0); 
alureginp : IN bit_vector(7 downto 0); 
b4outinp : IN bit_vector(7 downto 0);
clock4 : IN BIT;
reset4 : IN BIT;
ir5out : OUT bit_vector(15 downto 0); 
alucalout : OUT bit_vector(7 downto 0); 
datamemout : OUT bit_vector(7 downto 0);
memwriteenable : OUT BIT
);
END COMPONENT;


COMPONENT writeback 
PORT (
insir5out : IN bit_vector(15 downto 0);
alucalval : IN bit_vector(7 downto 0); 
memoutdata : IN bit_vector(7 downto 0);
clock5 : IN BIT;
reset5 : IN BIT;
writebackval : OUT bit_vector(7 downto 0);
writebackreg : OUT bit_vector(2 downto 0);
writebackena : OUT BIT
);
END COMPONENT;

-- the following components are used to forward the result bits to the output ports
COMPONENT forwardtoout 
PORT (
inputvector : IN bit_vector(7 downto 0);
outputvector : OUT bit_vector(7 downto 0)
);
END COMPONENT;

COMPONENT forwardbit 
PORT (
inputval : IN BIT;
outputVAL : OUT BIT
);
END COMPONENT;

COMPONENT fwd3 
PORT (
input : IN BIT_VECTOR(2 downto 0);
output: OUT bit_vector(7 downto 0)
);
END COMPONENT;


COMPONENT bitconv 
PORT (
bit1 : IN BIT;
bit2 : IN BIT;
bit3 : IN BIT;
outvec : OUT bit_vector(2 downto 0)
);
END COMPONENT;


--signal declaration for instruction fetch unit
SIGNAL instfetinp1 : bit_vector(7 downto 0);
SIGNAL instfetinp3 : bit;
SIGNAL instfetir : bit_vector(15 downto 0);
SIGNAL instfetpc : bit_vector(7 downto 0);
SIGNAL instfeten : bit;

--signal declaration for instruction decode unit
SIGNAL instdecinp4 : bit_vector(2 downto 0);
SIGNAL instdecinp5 : bit_vector(7 downto 0);
SIGNAL instdecir : bit_vector(15 downto 0);
SIGNAL instdecaval : bit_vector(7 downto 0);
SIGNAL instdecbval : bit_vector(7 downto 0);
SIGNAL instdecimm : bit_vector(7 downto 0);

--signal declaration for instruction execution unit
SIGNAL instexecir : bit_vector(15 downto 0);
SIGNAL instexecbval : bit_vector(7 downto 0);
SIGNAL instexealuout : bit_vector(7 downto 0);

--signal declaration for memory access unit
SIGNAL memaccir : bit_vector(15 downto 0);
SIGNAL datamemoutval : bit_vector(7 downto 0);
SIGNAL memaccout : bit_vector(7 downto 0);
SIGNAL memwrienable : BIT;

BEGIN

-- instruction fetch unit
instfetchunit : instfetch PORT MAP(instfetinp1,instruction,instfetinp3,reset,clock,instfetir,instfetpc);

-- instruction decode unit
instdecodeunit : instdecode PORT MAP(instfetpc,instfetir,clock,instdecinp4,instdecinp5,instfeten,reset,instfetinp3,instdecir,instdecaval,instdecbval,instdecimm,instfetinp1);

-- instruction execution unit
instrexecunit : instexec PORT MAP(instdecir,instdecaval,instdecbval,instdecimm,clock,reset,instexecbval,instexecir,instexealuout);

--memory access unit
memaccessunit : memaccess PORT MAP(instexecir,readdata,instexealuout,instexecbval,clock,reset,memaccir,memaccout,datamemoutval,memwrienable);

--writback unit
writeback : writeback PORT MAP(memaccir,memaccout,datamemoutval,clock,reset,instdecinp5,instdecinp4,instfeten);

-- forwarding signals to output ports
fwdwritedata : forwardtoout PORT MAP(instexecbval,writedata);
fwdwriteadd  : forwardtoout PORT MAP(instexealuout,memaddr);
fwdirnstadd  : forwardtoout PORT MAP(instfetpc,instadd);
fwdenablebit : forwardbit PORT MAP(memwrienable,memorywriteenable);


end;