wbreg.vbe

来自「i need of vhdl code for 32-bit risc proc」· VBE 代码 · 共 29 行

ENTITY wbreg IS
PORT (
Din5 : IN bit_vector(2 downto 0);
clk5 : IN BIT;
enable5 : IN BIT;
resetv : IN BIT;
Dout5 : OUT bit_vector(2 downto 0)
);
END wbreg;

ARCHITECTURE wbreg_arch OF wbreg IS

SIGNAL Reg5 : REG_VECTOR (2 downto 0) REGISTER;

BEGIN
flip_flop : BLOCK ( clk5='1' AND NOT clk5'STABLE AND enable5='1')

BEGIN
Reg5(0) <= GUARDED ( Din5(0) AND (NOT(resetv)) );
Reg5(1) <= GUARDED ( Din5(1) AND (NOT(resetv)) );
Reg5(2) <= GUARDED ( Din5(2) AND (NOT(resetv)) );

END BLOCK;

Dout5(0) <= Reg5(0);
Dout5(1) <= Reg5(1);
Dout5(2) <= Reg5(2);

END;