bitreg.vbe

来自「i need of vhdl code for 32-bit risc proc」· VBE 代码 · 共 27 行

-- Single Bit Register component
ENTITY bitreg IS
PORT (
bitin : IN BIT;
clk3 : IN BIT;
enable3 : IN BIT;
resetin : IN BIT;
bitout : OUT BIT
);
END bitreg;

ARCHITECTURE bitreg_arch OF bitreg IS

SIGNAL Reg3 : REG_BIT REGISTER;

BEGIN

flip_flop : BLOCK ( clk3='1' AND NOT clk3'STABLE AND enable3='1') 

BEGIN
Reg3 <= GUARDED ( bitin AND (NOT(resetin)) );

END BLOCK;

bitout <= Reg3;

END;