bit5mult.vst

i need of vhdl code for 32-bit risc processor

ENTITY bit5mult IS
PORT (
ainp : IN bit_vector(4 downto 0);
binp : IN bit_vector(4 downto 0);
result : OUT bit_vector(4 downto 0)
);
END bit5mult;

ARCHITECTURE bit5mult_arch OF bit5mult IS 

COMPONENT and5
PORT (
an1 : IN bit_vector(4 downto 0);
an2 : IN bit_vector(4 downto 0);
aout : OUT bit_vector(4 downto 0)
);
END COMPONENT;

COMPONENT bitextend 
PORT (
inpbit : IN BIT;
outvec : OUT BIT_VECTOR(4 downto 0)
);
END COMPONENT;

COMPONENT rightshift 
PORT (
inpbit : IN bit;
inpvec : IN bit_vector(4 downto 0);
shresult : OUT bit_vector(4 downto 0)
);
END COMPONENT;

COMPONENT fulladd 
PORT (
aval : IN bit_vector(4 downto 0);
bval: IN bit_vector(4 downto 0);
res : OUT bit_vector(4 downto 0);
carrout : OUT BIT
);
END COMPONENT;


COMPONENT buffer0
PORT (
bo1 : IN BIT;
bo2 : OUT BIT
);
END COMPONENT;

SIGNAL zerosig : BIT;
SIGNAL car1 : BIT;
SIGNAL car2 : BIT;
SIGNAL car3 : BIT;
SIGNAL car4 : BIT;
SIGNAL car5 : BIT;

SIGNAL res1 : BIT_VECTOR(4 downto 0);
SIGNAL res2 : BIT_VECTOR(4 downto 0);
SIGNAL res3 : BIT_VECTOR(4 downto 0);
SIGNAL res4 : BIT_VECTOR(4 downto 0);
SIGNAL res5 : BIT_VECTOR(4 downto 0);

SIGNAL p1 : BIT_VECTOR(4 downto 0);
SIGNAL p2 : BIT_VECTOR(4 downto 0);
SIGNAL p3 : BIT_VECTOR(4 downto 0);
SIGNAL p4 : BIT_VECTOR(4 downto 0);
SIGNAL p5 : BIT_VECTOR(4 downto 0);

SIGNAL seq1 : BIT_VECTOR(4 downto 0);
SIGNAL seq2 : BIT_VECTOR(4 downto 0);
SIGNAL seq3 : BIT_VECTOR(4 downto 0);
SIGNAL seq4 : BIT_VECTOR(4 downto 0);
SIGNAL seq5 : BIT_VECTOR(4 downto 0);

SIGNAL andres1 : BIT_VECTOR(4 downto 0);
SIGNAL andres2 : BIT_VECTOR(4 downto 0);
SIGNAL andres3 : BIT_VECTOR(4 downto 0);
SIGNAL andres4 : BIT_VECTOR(4 downto 0);
SIGNAL andres5 : BIT_VECTOR(4 downto 0);


BEGIN

buffer0 : buffer0 PORT MAP(ainp(0),zerosig);

bitextend0 : bitextend PORT MAP(zerosig,p1);

bitextend1 :  bitextend PORT MAP(ainp(0),seq1);
and51 : and5 PORT MAP(binp, seq1,andres1);
fulladd1 : fulladd PORT MAP(andres1,p1,res1,car1);
rightshift1 : rightshift PORT MAP(car1,res1,p2);

bitextend2 :  bitextend PORT MAP(ainp(1),seq2);
and52 : and5 PORT MAP(binp, seq2,andres2);
fulladd2 : fulladd PORT MAP(andres2,p2,res2,car2);
rightshift2 : rightshift PORT MAP(car2,res2,p3);

bitextend3 :  bitextend PORT MAP(ainp(2),seq3);
and53 : and5 PORT MAP(binp, seq3,andres3);
fulladd3 : fulladd PORT MAP(andres3,p3,res3,car3);
rightshift3 : rightshift PORT MAP(car3,res3,p4);

bitextend4 :  bitextend PORT MAP(ainp(3),seq4);
and54 : and5 PORT MAP(binp, seq4,andres4);
fulladd4 : fulladd PORT MAP(andres4,p4,res4,car4);
rightshift4 : rightshift PORT MAP(car4,res4,p5);

bitextend5 :  bitextend PORT MAP(ainp(4),seq5);
and55 : and5 PORT MAP(binp, seq5,andres5);
fulladd5 : fulladd PORT MAP(andres5,p5,res5,car5);
rightshift5 : rightshift PORT MAP(car5,res5,result);

end;