instdecode.vst

i need of vhdl code for 32-bit risc processor

ENTITY instdecode IS
PORT (
prcnt2out : IN bit_vector(7 downto 0);
insir2out : IN bit_vector(15 downto 0);
clock2 : IN BIT;
writeadd : IN bit_vector(2 downto 0);
writedata : IN bit_vector(7 downto 0);
writeen : IN BIT;
reset2 : IN BIT;
branchcond : OUT BIT;
ir3out : OUT bit_vector(15 downto 0);
a3out : OUT bit_vector(7 downto 0);
b3out : OUT bit_vector(7 downto 0);
imout : OUT bit_vector(7 downto 0);
newbranch : out bit_vector(7 downto 0)
);
END instdecode;

ARCHITECTURE instdecode_arch OF instdecode IS

COMPONENT pc
PORT (
Din2 : IN bit_vector(7 downto 0);
clk2 : IN BIT;
enable2 : IN BIT;
resetpc : IN BIT;
Dout2 : OUT bit_vector(7 downto 0)
);
END COMPONENT ;

COMPONENT instreg 
PORT (
Din1 : IN bit_vector(15 downto 0);
clk1 : IN BIT;
enable1 : IN BIT;
resetir : IN BIT;
Dout1 : OUT bit_vector(15 downto 0)
);
END COMPONENT ;

COMPONENT regfile 
PORT (
aadr: IN bit_vector(2 downto 0);
badr: IN bit_vector(2 downto 0);
wadr: IN bit_vector(2 downto 0);
wdata: IN bit_vector(7 downto 0);
wenable: IN BIT;
clock : IN BIT;
resetreg : IN BIT;
a : OUT bit_vector(7 downto 0);
b : OUT bit_vector(7 downto 0)
);
END COMPONENT;

COMPONENT cla 
PORT (
a : IN bit_vector(7 downto 0);
b : IN bit_vector(7 downto 0);
c0 : IN BIT;
s : OUT bit_vector(7 downto 0);
cout : OUT BIT
);
END COMPONENT ;

COMPONENT zerocheck 
PORT (
avalue : IN bit_vector(7 downto 0);
branchvalue : OUT BIT 
);
END COMPONENT;


COMPONENT bitconv 
PORT (
bit1 : IN BIT;
bit2 : IN BIT;
bit3 : IN BIT;
outvec : OUT bit_vector(2 downto 0)
);
END COMPONENT;

COMPONENT bitreg 
PORT (
bitin : IN BIT;
clk3 : IN BIT;
enable3 : IN BIT;
resetin : IN BIT;
bitout : OUT BIT
);
END COMPONENT;

COMPONENT immextend 
PORT (
bitv1 : IN BIT;
bitv2 : IN BIT;
bitv3 : IN BIT;
outvector : OUT bit_vector(7 downto 0)
);
END COMPONENT;

COMPONENT mux2to1
PORT (
inp1 : IN BIT;
inp2 : IN BIT;
en : IN BIT;
outp : OUT BIT
);
END COMPONENT;

COMPONENT andgate 
PORT (
a2 : IN BIT;
b2 : IN BIT;
c2 : OUT BIT 
);
END COMPONENT;


COMPONENT orgate 
PORT (
a3 : IN BIT;
b3 : IN BIT;
c3 : OUT BIT 
);
END COMPONENT;

COMPONENT buffer0
PORT (
bo1 : IN BIT;
bo2 : OUT BIT
);
END COMPONENT;

COMPONENT notgate
PORT (
a4 : IN BIT;
c4 : OUT BIT
);
END COMPONENT;

COMPONENT buffer1 
PORT (
bu1 : IN BIT;
bu2 : OUT BIT
);
END COMPONENT;

SIGNAL onesig2 : BIT;
SIGNAL zerosig2 : BIT;
SIGNAL branchbit : BIT;
SIGNAL branchbitinv : BIT;
SIGNAL branco : BIT;
SIGNAL finalbranch : BIT;
SIGNAL temp13 : BIT;
SIGNAL temp14 :BIT;
SIGNAL tempadd : BIT;
SIGNAL mux2a : BIT;
SIGNAL ormux4 : BIT;
SIGNAL mux2b : BIT;
SIGNAL newbranch1 : BIT_VECTOR( 7 downto 0);
SIGNAL jmpbrtemp : BIT;
SIGNAL firstbitinv : BIT;
SIGNAL carry2 : BIT;
SIGNAL inv12 : BIT;
SIGNAL and1215 : BIT;
SIGNAL and1312 : BIT;
SIGNAL first : BIT;
SIGNAL second : BIT;
SIGNAL branchfind : BIT;
SIGNAL bitconv1 : BIT_VECTOR(2 downto 0);
SIGNAL bitconv2 : BIT_VECTOR(2 downto 0);
SIGNAL a3regin : BIT_VECTOR(7 downto 0);
SIGNAL b3regin : BIT_VECTOR(7 downto 0);
SIGNAL a3regintemp : BIT_VECTOR(7 downto 0);
SIGNAL immval : BIT_VECTOR(2 downto 0);
SIGNAL imouttemp : BIT_VECTOR(7 downto 0);
SIGNAL addout2 : BIT_VECTOR(7 downto 0);
SIGNAL brancofin : BIT;
SIGNAL orval1 : BIT;
SIGNAL orval2 : BIT;
SIGNAL jmpbrtemp1 : BIT;


BEGIN

--Buffer doesnot operate on the input.it always outputs 1
buffer1_1 : buffer1 PORT MAP(clock2,onesig2);
buffer0_2 : buffer0 PORT MAP(clock2,zerosig2);

ir3 : instreg PORT MAP(insir2out,clock2,onesig2,reset2,ir3out);

bitconv1 : bitconv PORT MAP(insir2out(0),insir2out(1),insir2out(2),bitconv1);
bitconv2 : bitconv PORT MAP(insir2out(3),insir2out(4),insir2out(5),bitconv2);

regfile : regfile PORT MAP(bitconv2,bitconv1,writeadd,writedata,writeen,clock2,reset2,a3regin,b3regin);

--adding mux no2
--using values inv of 12, 14 from not gate below..
andmux21 :  andgate PORT MAP(inv12,temp14,mux2a);
andmux22 :  andgate PORT MAP(insir2out(13),insir2out(15),mux2b);
andmux23 :  andgate PORT MAP(mux2a,mux2b,ormux4);
mux2to1_2a : mux2to1 PORT MAP(a3regin(0),zerosig2,ormux4,a3regintemp(0));
mux2to1_2b : mux2to1 PORT MAP(a3regin(1),zerosig2,ormux4,a3regintemp(1));
mux2to1_2c : mux2to1 PORT MAP(a3regin(2),zerosig2,ormux4,a3regintemp(2));
mux2to1_2d : mux2to1 PORT MAP(a3regin(3),zerosig2,ormux4,a3regintemp(3));
mux2to1_2e : mux2to1 PORT MAP(a3regin(4),zerosig2,ormux4,a3regintemp(4));
mux2to1_2f : mux2to1 PORT MAP(a3regin(5),zerosig2,ormux4,a3regintemp(5));
mux2to1_2g : mux2to1 PORT MAP(a3regin(6),zerosig2,ormux4,a3regintemp(6));
mux2to1_2h : mux2to1 PORT MAP(a3regin(7),zerosig2,ormux4,a3regintemp(7));


a3 : pc PORT MAP(a3regintemp,clock2,onesig2,reset2,a3out);
b3 : pc PORT MAP(b3regin,clock2,onesig2,reset2,b3out);

-- Immediate part
orimm : orgate PORT MAP(zerosig2,insir2out(0),immval(0));
orimm2 : orgate PORT MAP(zerosig2,insir2out(1),immval(1));
orimm3 : orgate PORT MAP(zerosig2,insir2out(2),immval(2));


immextend : immextend PORT MAP(immval(2),immval(1),immval(0),imouttemp);


im : pc PORT MAP(imouttemp,clock2,onesig2,reset2,imout);

--modified pipeline changes
zerocheck : zerocheck PORT MAP(a3regin,branchbit);

--not zero conditon

notgate : notgate PORT MAP(branchbit,branchbitinv);
mux2to1_1 : mux2to1 PORT MAP(branchbitinv,branchbit,insir2out(12),finalbranch);
andgate : andgate PORT MAP(finalbranch,branchfind,branco);
orgt : orgate PORT MAP(branco,jmpbrtemp,brancofin);

bitregco : bitreg PORT MAP(brancofin,clock2,onesig2,reset2,branchcond);

--finding branchfind bit
notgate7 : notgate PORT MAP(insir2out(12),inv12);
and11: andgate PORT MAP(firstbitinv,inv12,and1215);
and12 : andgate PORT MAP(and1215,insir2out(13),second);
and13 : andgate PORT MAP(insir2out(12),insir2out(13),and1312);
and14 : andgate PORT MAP(and1312,insir2out(15),first);
orfinal : orgate PORT MAP(first,second,branchfind);

--TO differentiate between jump and branch
notgate2 : notgate PORT MAP(insir2out(13),temp13);
notgate3 : notgate PORT MAP(insir2out(14),temp14);
andgate2 : andgate PORT MAP(temp13,temp14,tempadd);
notgate4 : notgate PORT MAP(insir2out(15),firstbitinv);
andgate3 : andgate PORT MAP(tempadd,firstbitinv,jmpbrtemp1);
orgate2: orgate PORT MAP(insir2out(3),insir2out(4),orval1);
orgate3: orgate PORT MAP(insir2out(5),orval1,orval2);
andgatean : andgate PORT MAP(orval2,jmpbrtemp1,jmpbrtemp);

claforbranchtargetcalc : cla PORT MAP(prcnt2out,imouttemp,zerosig2,addout2,carry2);


mux2to1_21 : mux2to1 PORT MAP(addout2(0),insir2out(0),jmpbrtemp,newbranch1(0));
mux2to1_22 : mux2to1 PORT MAP(addout2(1),insir2out(1),jmpbrtemp,newbranch1(1));
mux2to1_23 : mux2to1 PORT MAP(addout2(2),insir2out(2),jmpbrtemp,newbranch1(2));
mux2to1_24 : mux2to1 PORT MAP(addout2(3),insir2out(3),jmpbrtemp,newbranch1(3));
mux2to1_25 : mux2to1 PORT MAP(addout2(4),insir2out(4),jmpbrtemp,newbranch1(4));
mux2to1_26 : mux2to1 PORT MAP(addout2(5),insir2out(5),jmpbrtemp,newbranch1(5));
mux2to1_27 : mux2to1 PORT MAP(addout2(6),insir2out(6),jmpbrtemp,newbranch1(6));
mux2to1_28 : mux2to1 PORT MAP(addout2(7),insir2out(7),jmpbrtemp,newbranch1(7));

newbr :  pc PORT MAP(newbranch1,clock2,onesig2,reset2,newbranch);

END;