finalleft.vst

i need of vhdl code for 32-bit risc processor

ENTITY finalleft IS
PORT(
inve : IN BIT_VECTOR(4 downto 0);
val1: OUT BIT_VECTOR(4 downto 0);
val2: OUT BIT_VECTOR(4 downto 0);
val3: OUT BIT_VECTOR(4 downto 0);
val4: OUT BIT_VECTOR(4 downto 0)
);
END finalleft;

ARCHITECTURE finalleft_arch OF finalleft IS

COMPONENT leftshift
PORT (
inpbit1 : IN bit;
inpvec1 : IN bit_vector(4 downto 0);
shresult1 : OUT bit_vector(4 downto 0)
);
END COMPONENT;

COMPONENT buffer0
PORT (
bo1 : IN BIT;
bo2 : OUT BIT
);
END COMPONENT;

SIGNAL val1a : BIT_VECTOR(4 downto 0);
SIGNAL val2a : BIT_VECTOR(4 downto 0);
SIGNAL val3a : BIT_VECTOR(4 downto 0);
SIGNAL zerov : BIT;


BEGIN

buffer0a : buffer0 PORT MAP(inve(0),zerov);

leftshift1 : leftshift PORT MAP(zerov,inve,val1);
leftshift1a : leftshift PORT MAP(zerov,inve,val1a);
leftshift2 : leftshift PORT MAP(zerov,val1a,val2);
leftshift2a: leftshift PORT MAP(zerov,val1a,val2a);
leftshift3 : leftshift PORT MAP(zerov,val2a,val3);
leftshift3a: leftshift PORT MAP(zerov,val2a,val3a);
leftshift4 : leftshift PORT MAP(zerov,val3a,val4);

end;