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These files are written by me. By downloading these files you are agreeing that you cannot hold me responsible for use/misuse of the files.Details regarding the project:These files are written for asimut(a subset of VHDL). So I cannot guarantee that these files can be used in any other VHDL product. To get full utilization of the code you may have to use asimut. It is available free of cost and can be downloaded from http://www-asim.lip6.fr . Online documentation is also available for this tool. I guess these files can be converted using a tool to be used in Cadence. You can try that too.I regret for not providing proper documentation and comments for these files. The names of the files are self-describing. The main file that instantiates all the components and make the complete DLX pipelined processor is processor.vst. The test patterns are processorpattern.pat.-Kaarthik Sivashanmugam(s_kaarthik@hotmail.com)to execute the project in gemini.cs.uga.edu, you can use following commands setenv MBK_IN_LO vst setenv MBK_CATAL_NAME catal~bishop/alliance/archi/Solaris/bin/asimut -c xxxx ( for vst file )or~bishop/alliance/archi/Solaris/bin/asimut -c -b xxxx ( for vbe file )~bishop/alliance/archi/Solaris/bin/asimut -c xxxx yyyy zzzzzxxxx vbe or vst fileyyyy pat filezzzz res pat file
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