cla.vst

i need of vhdl code for 32-bit risc processor

ENTITY cla IS
PORT (
a : IN bit_vector(7 downto 0);
b : IN bit_vector(7 downto 0);
c0 : IN BIT;
s : OUT bit_vector(7 downto 0);
cout : OUT BIT
);
END cla ;

ARCHITECTURE cla_arch OF cla IS

-- Components to be used in the Structural Description of CLA is defined here

-- all these components are listed in catalog file

-- FA block as a component. Behavioral description in fa_block.vbe

COMPONENT fa_block
PORT ( ai : IN BIT;
       bi : IN BIT;
       cia : IN BIT;
       si : OUT BIT;
       gi : OUT BIT;
       pi : OUT BIT
 );
END COMPONENT;


-- Component that computes P and G. Behavioral Description in fb_block.vbe
 
COMPONENT fb_block
PORT ( gij : IN BIT;
       pij : IN BIT;
       cib : IN BIT;
       gj1k : IN BIT;
       pj1k : IN BIT;
       cio : OUT BIT;
       cj1 : OUT BIT;
       gik : OUT BIT;
       pik : OUT BIT
 );
END COMPONENT;


-- AND gate. Behavioral description is in andgate.vbe

COMPONENT andgate
PORT ( a2 : IN BIT;
       b2 : IN BIT;
       c2 : OUT BIT 
);
END COMPONENT;


-- OR gate. Behavioral Description is in orgate.vbe

COMPONENT orgate
PORT ( a3 : IN BIT;
       b3 : IN BIT;
       c3 : OUT BIT 
);
END COMPONENT;

-- Intermediate values are to be assigned to some signals. Declaraion of Signals follows

SIGNAL gv : bit_vector(7 downto 0);
SIGNAL pv : bit_vector(7 downto 0);
SIGNAL gv1 : bit_vector(6 downto 0);
SIGNAL pv1 : bit_vector(6 downto 0);
SIGNAL c : bit_vector(7 downto 0);
SIGNAL cisb : bit_vector(5 downto 0);
SIGNAL pc : BIT;

BEGIN

-- Instantiation of 8 FA components 
A_0 : fa_block PORT MAP(ai=>a(0),bi=>b(0),cia=>c0,si=>s(0),gi=>gv(0),pi=>pv(0));
A_1 : fa_block PORT MAP(ai=>a(1),bi=>b(1),cia=>c(1),si=>s(1),gi=>gv(1),pi=>pv(1));
A_2 : fa_block PORT MAP(ai=>a(2),bi=>b(2),cia=>c(2),si=>s(2),gi=>gv(2),pi=>pv(2));
A_3 : fa_block PORT MAP(ai=>a(3),bi=>b(3),cia=>c(3),si=>s(3),gi=>gv(3),pi=>pv(3));
A_4 : fa_block PORT MAP(ai=>a(4),bi=>b(4),cia=>c(4),si=>s(4),gi=>gv(4),pi=>pv(4));
A_5 : fa_block PORT MAP(ai=>a(5),bi=>b(5),cia=>c(5),si=>s(5),gi=>gv(5),pi=>pv(5));
A_6 : fa_block PORT MAP(ai=>a(6),bi=>b(6),cia=>c(6),si=>s(6),gi=>gv(6),pi=>pv(6));
A_7 : fa_block PORT MAP(ai=>a(7),bi=>b(7),cia=>c(7),si=>s(7),gi=>gv(7),pi=>pv(7));


-- Instantiation of 7 fb_blocks
B_0 : fb_block PORT 
MAP(gij=>gv(0),pij=>pv(0),cib=>cisb(2),gj1k=>gv(1),pj1k=>pv(1),cio=>c(0),cj1=>c(1),gik=>gv1(0),pik=>pv1(0));
B_1 : fb_block PORT MAP(gv(2),pv(2),cisb(3),gv(3),pv(3),c(2),c(3),gv1(1),pv1(1));
B_2 : fb_block PORT MAP(gv(4),pv(4),cisb(4),gv(5),pv(5),c(4),c(5),gv1(2),pv1(2));
B_3 : fb_block PORT MAP(gv(6),pv(6),cisb(5),gv(7),pv(7),c(6),c(7),gv1(3),pv1(3));
B_4 : fb_block PORT MAP(gv1(0),pv1(0),cisb(0),gv1(1),pv1(1),cisb(2),cisb(3),gv1(4),pv1(4));
B_5 : fb_block PORT MAP(gv1(2),pv1(2),cisb(1),gv1(3),pv1(3),cisb(4),cisb(5),gv1(5),pv1(5));
B_6 : fb_block PORT MAP(gv1(4),pv1(4),c0,gv1(5),pv1(5),cisb(0),cisb(1),gv1(6),pv1(6));

-- To generate the output carry AND and OR gates are used
-- Instantiation of AND gate
andgate1 : andgate PORT MAP(pv1(6),c(0),pc);

-- Instantiation of OR gate
orgate1  : orgate PORT MAP(pc,gv1(6),cout);

END;