ifnegate.vst

i need of vhdl code for 32-bit risc processor

ENTITY ifnegate IS
PORT(
s1 : IN BIT;
s2 : IN BIT;
oper2 : IN BIT_VECTOR (4 downto 0);
newop2 : OUT BIT_VECTOR ( 4 downto 0)
);
END ifnegate;

ARCHITECTURE ifnegate_arch OF ifnegate IS

COMPONENT fulladd
PORT (
aval : IN bit_vector(4 downto 0);
bval : IN bit_vector(4 downto 0);
res : OUT bit_vector(4 downto 0);
carrout : OUT BIT
);
END COMPONENT;

COMPONENT outvec1
PORT(
i1 : IN BIT;
outv : OUT BIT_VECTOR (4 downto 0)
);
END COMPONENT;

COMPONENT notgate
PORT (
a4 : IN BIT;
c4 : OUT BIT
);
END COMPONENT;

COMPONENT xorgate2
PORT (
a8 : IN BIT;
b8 : IN BIT;
d8 : OUT BIT
);
END COMPONENT;

COMPONENT mux2to1
PORT (
inp1 : IN BIT;
inp2 : IN BIT;
en : IN BIT;
outp : OUT BIT
);
END COMPONENT;

SIGNAL oper2inv : BIT_VECTOR( 4 downto 0);
SIGNAL addend : BIT_VECTOR( 4 downto 0);
SIGNAL twocomp : BIT_VECTOR( 4 downto 0);

SIGNAL  diff : BIT;
SIGNAL carry : BIT;

BEGIN

xor0 : xorgate2 PORT MAP(s1,s2,diff);

outvec1 : outvec1 PORT MAP(diff,addend);

not1 : notgate PORT MAP(oper2(0),oper2inv(0));
not2 : notgate PORT MAP(oper2(1),oper2inv(1));
not3 : notgate PORT MAP(oper2(2),oper2inv(2));
not4 : notgate PORT MAP(oper2(3),oper2inv(3));
not5 : notgate PORT MAP(oper2(4),oper2inv(4));

fulladd : fulladd PORT MAP(addend,oper2inv,twocomp,carry);


mux2to1a  : mux2to1 PORT MAP(oper2(0),twocomp(0),diff,newop2(0));
mux2to1a1 : mux2to1 PORT MAP(oper2(1),twocomp(1),diff,newop2(1));
mux2to1a2 : mux2to1 PORT MAP(oper2(2),twocomp(2),diff,newop2(2));
mux2to1a3 : mux2to1 PORT MAP(oper2(3),twocomp(3),diff,newop2(3));
mux2to1a4 : mux2to1 PORT MAP(oper2(4),twocomp(4),diff,newop2(4));


end;