regwrenearlier.vbe

i need of vhdl code for 32-bit risc processor

ENTITY regwren IS
PORT (
inputval : IN BIT_VECTOR(15 downto 0);
outputval: OUT BIT
);
END regwren;

ARCHITECTURE regwren_arch OF regwren IS

BEGIN


 outputval <=(( NOT(inputval(15)) AND NOT(inputval(14)) AND inputval(13)      AND inputval(12)         AND  NOT( (inputval(9) AND inputval(10)) AND inputval(11) ) ) OR
              ( inputval(15)      AND NOT(inputval(14)) AND inputval(13)      AND  NOT(inputval(12)) )                          OR 
              ( inputval(15)      AND inputval(14)      AND NOT(inputval(13)) )  );	

END;