嵌入式系统的TCP/IP源代码

          Programmable Interval Timer (PIT)
 060-06F
          Keyboard Controller
 070-071
          Real Time Clock
 080-083
          DMA Page Register
 090-097
          Programmable Option Select (PS/2)
 0A0-0AF
          PIC #2
 0C0-0CF
          DMAC #2
 0E0-0EF
          reserved
 0F0-0FF
          Math coprocessor, PCJr Disk Controller
 100-10F
          Programmable Option Select (PS/2)
 110-16F
          AVAILABLE
 170-17F
          Hard Drive 1 (AT)
 180-1EF
          AVAILABLE
 1F0-1FF
          Hard Drive 0 (AT)
 200-20F
          Game Adapter
 210-217
          Expansion Card Ports
 220-26F
          AVAILABLE
 278-27F
          Parallel Port 3
 280-2A1
          AVAILABLE
 2A2-2A3
          clock
 2B0-2DF
          EGA/Video
 2E2-2E3
          Data Acquisition Adapter (AT)
 2E8-2EF
          Serial Port COM4
 2F0-2F7
          Reserved
 2F8-2FF
          Serial Port COM2
 300-31F
          Prototype Adapter, Periscope Hardware Debugger
 320-32F
          AVAILABLE
 330-33F
          Reserved for XT/370
 340-35F
          AVAILABLE
 360-36F
          Network
 370-377
          Floppy Disk Controller
 378-37F
          Parallel Port 2
 380-38F
          SDLC Adapter
 390-39F
          Cluster Adapter
 3A0-3AF
          reserved
 3B0-3BF
          Monochome Adapter
 3BC-3BF
          Parallel Port 1
 3C0-3CF
          EGA/VGA
 3D0-3DF
          Color Graphics Adapter (CGA)
 3E0-3EF
          Serial Port COM3
 3F0-3F7
          Floppy Disk Controller
 3F8-3FF
          Serial Port COM1


Soundblaster cards usually use I/O ports 220-22F. 

Data acquisition cards frequently use 300-320. 

Memory Addresses

 00000-9FFFF
              System RAM (640k)
 A0000-AFFFF
              EGA/VGA Video RAM
 B0000-BFFFF
              Hercules/Mono/CGA Video RAM
 C0000-C7FFF
              Video ROM
 C8000-CFFFF
              Hard drive adapter BIOS ROM
 D0000-D7FFF
              I/O Expansion ROM (unused on most systems)
 D8000-DFFFF
              PC JR Cartridge (unused on most systems)
 E0000-EFFFF
              Expansion ROM (unused on some systems)
 F0000-FFFFF
              System ROM
 100000+
              System RAM (extended memory)


There is very little memory space available for ISA cards to use. Generally, most computers will let you have the D segment (or at least the lower half of the D
segment), and maybe the E segment, but nothing else. On newer systems, the D and E segment will usually contain RAM that must be disabled in the BIOS setup
before these memory areas may be used. It should be obvious from the above memory map that, unlike I/O addresses, all memory address lines must be decoded to
prevent bus collisions with other memory mapped devices. 

To create a rom that is recognized by the BIOS, the first two bytes must be 55 AA. The third byte must be the number of 512 byte blocks of address space used by
the ROM. The eight bit checksum for the ROM must also be zero. If all of these conditions are met, then your ROM will be executed when the system starts,
beginning execution at the byte immediately following the 512 byte block count. 

DMA Read and Write

The ISA bus uses two DMA controllers (DMAC) cascaded together. The slave DMAC connects to the master DMAC via DMA channel 4 (channel 0 on the
master DMAC). The slave therefore gains control of the bus through the master DMAC. On the ISA bus, the DMAC is programmed to use fixed priority (channel 0
always has the highest priority), which means that channel 0-4 from the slave have the highest priority (since they connect to the master channel 0), followed by
channels 5-7 (which are channel 1-3 on the master). 

The DMAC can be programmed for read transfers (data is read from memory and written to the I/O device), write transfers (data is read from the I/O device and
written to memory), or verify transfers (neither a read or a write - this was used by DMA CH0 for DRAM refresh on early PCs). 

Before a DMA transfer can take place, the DMA Controller (DMAC) must be programmed. This is done by writing the start address and the number of bytes to
transfer (called the transfer count) and the direction of the transfer to the DMAC. After the DMAC has been programmed, the device may activate the appropriate
DMA request (DRQx) line. 

Slave DMA Controller

  I/O
                                                             Port
 0000
      DMA CH0 Memory Address Register
      Contains the lower 16 bits of the memory address, written as two consecutive bytes.
 0001
      DMA CH0 Transfer Count
      Contains the lower 16 bits of the transfer count, written as two consecutive bytes.
 0002
      DMA CH1 Memory Address Register
 0003
      DMA CH1 Transfer Count
 0004
      DMA CH2 Memory Address Register
 0005
      DMA CH2 Transfer Count
 0006
      DMA CH3 Memory Address Register
 0007
      DMA CH3 Transfer Count
 0008
      DMAC Status/Control Register
      Status (I/O read) bits 0-3: Terminal Count, CH 0-3
      - bits 4-7: Request CH0-3
      Control (write)
      - bit 0: Mem to mem enable (1 = enabled)
      - bit 1: ch0 address hold enable (1 = enabled)
      - bit 2: controller disable (1 = disabled)
      - bit 3: timing (0 = normal, 1 = compressed)
      - bit 4: priority (0 = fixed, 1 = rotating)
      - bit 5: write selection (0 = late, 1 = extended)
      - bit 6: DRQx sense asserted (0 = high, 1 = low)
      - bit 7: DAKn sense asserted (0 = low, 1 = high)
 0009
      Software DRQn Request
      - bits 0-1: channel select (CH0-3)
      - bit 2: request bit (0 = reset, 1 = set)
 000A
      DMA mask register
      - bits 0-1: channel select (CH0-3)
      - bit 2: mask bit (0 = reset, 1 = set)
 000B
      DMA Mode Register
      - bits 0-1: channel select (CH0-3)
      - bits 2-3: 00 = verify transfer, 01 = write transfer, 10 = read transfer, 11 = reserved
      - bit 4: Auto init (0 = disabled, 1 = enabled)
      - bit 5: Address (0 = increment, 1 = decrement)
      - bits 6-7: 00 = demand transfer mode, 01 = single transfer mode, 10 = block transfer mode, 11 = cascade mode
 000C
      DMA Clear Byte Pointer
      Writing to this causes the DMAC to clear the pointer used to keep track of 16 bit data transfers into and out of the DMAC for hi/low byte sequencing.
 000D
      DMA Master Clear (Hardware Reset)
 000E
      DMA Reset Mask Register - clears the mask register
 000F
      DMA Mask Register
      - bits 0-3: mask bits for CH0-3 (0 = not masked, 1 = masked)
 0081
      DMA CH2 Page Register (address bits A16-A23)
 0082
      DMA CH3 Page Register
 0083
      DMA CH1 Page Register
 0087
      DMA CH0 Page Register
 0089
      DMA CH6 Page Register
 008A
      DMA CH7 Page Register
 008B
      DMA CH5 Page Register


Master DMA Controller

  I/O
                                                             Port
 00C0
       DMA CH4 Memory Address Register
       Contains the lower 16 bits of the memory address, written as two consecutive bytes.
 00C2
       DMA CH4 Transfer Count
       Contains the lower 16 bits of the transfer count, written as two consecutive bytes.
 00C4
       DMA CH5 Memory Address Register
 00C6
       DMA CH5 Transfer Count
 00C8
       DMA CH6 Memory Address Register
 00CA
       DMA CH6 Transfer Count
 00CC
       DMA CH7 Memory Address Register
 00CE
       DMA CH7 Transfer Count
 00D0
       DMAC Status/Control Register
       Status (I/O read) bits 0-3: Terminal Count, CH 4-7
       - bits 4-7: Request CH4-7
       Control (write)- bit 0: Mem to mem enable (1 = enabled)
       - bit 1: ch0 address hold enable (1 = enabled)
       - bit 2: controller disable (1 = disabled)
       - bit 3: timing (0 = normal, 1 = compressed)
       - bit 4: priority (0 = fixed, 1 = rotating)
       - bit 5: write selection (0 = late, 1 = extended)
       - bit 6: DRQx sense asserted (0 = high, 1 = low)
       - bit 7: DAKn sense asserted (0 = low, 1 = high)
 00D2
       Software DRQn Request
       - bits 0-1: channel select (CH4-7)
       - bit 2: request bit (0 = reset, 1 = set)
 00D4
       DMA mask register
       - bits 0-1: channel select (CH4-7)
       - bit 2: mask bit (0 = reset, 1 = set)
 00D6
       DMA Mode Register
       - bits 0-1: channel select (CH4-7)
       - bits 2-3: 00 = verify transfer, 01 = write transfer, 10 = read transfer, 11 = reserved
       - bit 4: Auto init (0 = disabled, 1 = enabled)
       - bit 5: Address (0 = increment, 1 = decrement)
       - bits 6-7: 00 = demand transfer mode, 01 = single transfer mode, 10 = block transfer mode, 11 = cascade mode
 00D8
       DMA Clear Byte Pointer
       Writing to this causes the DMAC to clear the pointer used to keep track of 16 bit data transfers into and out of the DMAC for hi/low byte sequencing.
 00DA
       DMA Master Clear (Hardware Reset)
 00DC
       DMA Reset Mask Register - clears the mask register
 00DE
       DMA Mask Register
       - bits 0-3: mask bits for CH4-7 (0 = not masked, 1 = masked)


Single Transfer Mode:

The DMAC is programmed for transfer. The DMA device requests a transfer by driving the appropriate DRQ line high. The DMAC responds by asserting AEN
and acknowledges the DMA request through the appropriate DAK line. The I/O and memory command lines are also asserted. When the DMA device sees the
DAK signal, it drops the DRQ line. The DMAC places the memory address on the SA bus (at the same time as the command lines are asserted), and the device
either reads from or writes to memory, depending on the type of transfer. The transfer count is incrimented, and the address incrimented/decrimented. DAK is
de-asserted. The cpu now once again has control of the bus, and continues execution until the I/O device is once again ready for transfer. The DMA device repeats
the procedure, driving DRQ high and waiting for DAK, then transferring data. This continues for a number of cycles equal to the transfer count. When this has been
completed, the DMAC signals the cpu that the DMA transfer is complete via the TC (terminal count) signal.  

Block Transfer Mode:

The DMAC is programmed for transfer. The device attempting DMA transfer drives the appropriate DRQ line high. The motherboard responds by driving AEN
high and DAK low. This indicates that the DMA device is now the bus master. In response to the DAK signal, the DMA device drops DRQ. T> 


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