嵌入式系统的TCP/IP源代码

THE ISA AND PC/104 BUS

IBM, IBM/XT, IBM PC, and IBM PC AT are registered trademarks of International Business Machines Corporation. 

This file is designed to give a basic overview of the bus found in most IBM clone computers, often referred to as the XT or AT bus. The AT version of the bus is
upwardly compatible, which means that cards designed to work on an XT bus will work on an AT bus. This bus was produced for many years without any formal
standard. In recent years, a more formal standard called the ISA bus (Industry Standard Architecture) has been created, with an extension called the EISA
(Extended ISA) bus also now as a standard. The EISA bus extensions will not be detailed here. 

This file is not intended to be a thorough coverage of the standard. It is for informational purposes only, and is intended to give designers and hobbyists sufficient
information to design their own XT and AT compatible cards. 

The IEEE P996 standard may be obtained from: 

     IEEE Standards Office
     445 Hoes Lane
     Piscataway, NJ 08854

The PC/104 standard may be obtained from: 

     The PC/104 Consortium
     PO Box 4303
     Mountain View, CA 94040

Connector Pinouts

ISA Connector

Component Side                  

A1:  *CHKCHK                    B1:  GND
A2:  SD7                        B2:  RESDRV
A3:  SD6                        B3:  +5 
A4:  SD5                        B4:  IRQ2
A5:  SD4                        B5:  -5 
A6:  SD3                        B6:  DRQ2
A7:  SD2                        B7:  -12 
A8:  SD1                        B8:  *NOWS  [A]
A9:  SD0                        B9:  +12
A10: CHRDY                      B10: GND
A11: AEN                        B11: *SMWTC
A12: SA19                       B12: *SMRDC
A13: SA18                       B13: *IOWC
A14: SA17                       B14: *IORC
A15: SA16                       B15: *DAK3
A16: SA15                       B16: DRQ3
A17: SA14                       B17: *DAK1
A18: SA13                       B18: DRQ1
A19: SA12                       B19: *REFRESH
A20: SA11                       B20: BCLK
A21: SA10                       B21: IRQ7
A22: SA9                        B22: IRQ6
A23: SA8                        B23: IRQ5
A24: SA7                        B24: IRQ4
A25: SA6                        B25: IRQ3
A26: SA5                        B26: *DAK2
A27: SA4                        B27: TC
A28: SA3                        B28: BALE
A29: SA2                        B29: +5 
A30: SA1                        B30: OSC
A31: SA0                        B31: GND


AT Bus only:

Component Side

C1:  *SBHE                      D1:  *M16
C2:  LA23                       D2:  *IO16
C3:  LA22                       D3:  IRQ10
C4:  LA21                       D4:  IRQ11
C5:  LA20                       D5:  IRQ12
C6:  LA19                       D6:  IRQ15 [B]
C7:  LA18                       D7:  IRQ14
C8:  LA17                       D8:  *DAK0
C9:  *MRDC                      D9:  DRQ0
C10: *MWTC                      D10: *DAK5
C11: SD8                        D11: DRQ5
C12: SD9                        D12: *DAK6
C13: SD10                       D13: DRQ65
C14: SD11                       D14: *DAK7
C15: SD12                       D15: DRQ7
C16: SD13                       D16: +5 
C17: SD14                       D17: *MASTER16
C18: SD15                       D18: GND


* Active Low 

[A] A signal called J8, or Card_Select was used on this pin on the IBM XT. This signal was only active on the J8 slot on the motherboard (the slot closest to the
keyboard connector). 

[B] Many texts (including earlier versions of mine) accidentally place IRQ13 on this pin. I'm not sure how IRQ15 managed to end up on the pin where IRQ13 fits in
the sequence (IRQ10-14), but it is easy to see how this causes numerous typographic errors. Note that IRQ13 (coprocessor) is not present on the ISA bus
connector.  

PC/104 Connector


PIN     ROW A (J1)     ROW B(J1)      ROW C (J2)     ROW D (J2)
----------------------------------------------------------------
 0                                    GND            GND
 1      *CHCHK         GND            *SBHE          *M16
 2      SD7            RESDRV         LA23           *IO16
 3      SD6            +5V            LA22           IRQ10
 4      SD5            IRQ9           LA21           IRQ11
 5      SD4            -5V            LA20           IRQ12
 6      SD3            DRQ2           LA19           IRQ15
 7      SD2            -12V           LA18           IRQ14
 8      SD1            *ENDXFR        LA17           *DACK0
 9      SD0            +12V           *MRDC          DRQ0
 10     CHRDY          KEY            *MWTC          *DACK5
 11     AEN            *SMWTC         SD8            DRQ5
 12     SA19           *SMRDC         SD9            *DACK6
 13     SA18           *IOWC          SD10           DRQ6
 14     SA17           *IORC          SD11           *DACK7
 15     SA16           *DACK3         SD12           DRQ7
 16     SA15           DRQ3           SD13           +5V
 17     SA14           *DACK1         SD14           *MASTER16
 18     SA13           DRQ1           SD15           GND
 19     SA12           *REFRESH       KEY            GND
 20     SA11           CLK
 21     SA10           IRQ7
 22     SA9            IRQ6
 23     SA8            IRQ5
 24     SA7            IRQ4
 25     SA6            IRQ3
 26     SA5            *DACK2
 27     SA4            TC
 28     SA3            BALE
 29     SA2            +5V
 30     SA1            OSC
 31     SA0            GND
 32     GND            GND

Rows C and D are used for 16 bit (AT) operation. 

Keys are missing pins and holes are filled. 

Electrical Characteristics:

The actual drive capabilities of ISA motherboards can vary greatly. 

The IEEE P996 specs 1.0 offers these guidelines: 

     +12V at 1.5A 
     -12V at 0.3A 
     +5V at 4.5A 
     -5V at 0.2A 

PC/104 specifies the following: 

     +12V at 1.0A 
     +5V at 2.0A 
     -5V at 0.2A 
     -12V at 0.3A 
     M16, IO16, MASTER16, and ENDXFR are 20 mA max. All other signals are 4 mA max. 

Signal Descriptions

     +5, -5, +12, -12: Power supplies. -5 is often not implimented. 
     AEN: Address Enable. This is asserted when a DMAC has control of the bus. This prevents an I/O device from responding to the I/O command lines during
     a DMA transfer. 
     BALE: Bus Address Latch Enable. The address bus is latched on the rising edge of this signal. The address on the SA bus is valid from the falling edge of
     BALE to the end of the bus cycle. Memory devices should latch the LA bus on the falling edge of BALE. Some references refer to this signal as Buffered
     Address Latch Enable, or just Address Latch Enable (ALE). 
     BCLK: Bus Clock, 33% Duty Cycle. Frequency Varies. 4.77 to 8 MHz typical. 8.3 MHz is specified as the maximum, but many systems allow this clock to
     be set to 12 MHz and higher. 
     CHCHK: Channel Check. A low signal generates an NMI. The NMI signal can be masked on a PC, externally to the processor (of course). Bit 7 of port
     70(hex) (enable NMI interrupts) and bit 3 of port 61 (hex) (recognition of channel check) must both be set to zero for an NMI to reach the cpu. 
     CHRDY: Channel Ready. Setting this low prevents the default ready timer from timing out. The slave device may then set it high again when it is ready to end
     the bus cycle. Holding this line low for too long (15 microseconds, typically) can prevent RAM refresh cycles on some systems. This signal is called
     IOCHRDY (I/O Channel Ready) by some references. CHRDY and NOWS should not be used simultaneously. This may cause problems with some bus
     controllers. 
     DAKx: DMA Acknowledge. 
     DRQx: DMA Request. 
     IO16: I/O size 16. Generated by a 16 bit slave when addressed by a bus master. 
     IORC: I/O Read Command line. 
     IOWC: I/O Write Command line. 
     IRQx: Interrupt Request. IRQ2 has the highest priority. IRQ 10-15 are only available on AT machines, and are higher priority than IRQ 3-7. 
     LAxx: Latchable Address lines. Combine with the lower address lines to form a 24 bit address space (16 MB) 
     MASTER16: 16 bit bus master. Generated by the ISA bus master when initiating a bus cycle. 
     M16: Memory Access, 16 bit 
     MRDC: Memory Read Command line. 
     MWTC: Memory Write Command line. 
     NOWS: No Wait State. Used to shorten the number of wait states generated by the default ready timer. This causes the bus cycle to end more quickly, since
     wait states will not be inserted. Most systems will ignore NOWS if CHRDY is active (low). However, this may cause problems with some bus controllers,
     and both signals should not be active simultaneously. 
     OSC: Oscillator, 14.318 MHz, 50% Duty Cycle. Frequency varies. This was originally divided by 3 to provide the 4.77 MHz cpu clock of early PCs, and
     divided by 12 to produce the 1.19 MHz system clock. Some references have placed this signal as low as 1 MHz (possibly referencing the system clock), but
     most modern systems use 14.318 MHz.
     This frequency (14.318 MHz) is four times the television colorburst frequency.
     Refresh timing on many PC's is based on OSC/18, or approximately one refresh cycle every 15 microseconds. Many modern motherboards allow this rate to
     be changed, which frees up some bus cycles for use by software, but also can cause memory errors if the system RAM cannot handle the slower refresh
     rates. 
     REFRESH: Refresh. Generated when the refresh logic is bus master. An ISA device acting as bus master may also use this signal to initiate a refresh cycle. 
     RESDRV: This signal goes momentarily high when the machine is powered up. Driving it high will force a system reset. 
     SA0-SA19: System Address Lines, tri-state. 
     SBHE: System Bus High Enable, tristate. Indicates a 16 bit data transfer. This may also indicate an 8 bit transfer using the upper half of the data bus (if an odd
     address is present). 
     SD0-SD15: System Data lines, or Standard Data Lines. They are bidrectional and tri-state. On most systems, the data lines float high when not driven. 
     SMRDC: Standard Memory Read Command line. Indicates a memory read in the lower 1 MB area. 
     SMWTC: Standard Memory Write Commmand line. Indicates a memory write in the lower 1 MB area. 
     TC: Terminal Count. Notifies the cpu that that the last DMA data transfer operation is complete. 

8 Bit Memory or I/O Transfer Timing Diagram (4 wait states shown)

                     

Note: W1 through W4 indicate wait cycles. 

BALE is placed high, and the address is latched on the SA bus. The slave device may safely sample the address during the falling edge of BALE, and the address on
the SA bus remains valid until the end of the transfer cycle. Note that AEN remains low throughout the entire transfer cycle. 

The command line is then pulled low (IORC or IOWC for I/O commands, SMRDSC or SMWTC for memory commands, read and write respectively). For write
operations, the data remaines on the SD bus for the remainder of the transfer cycle. For read operations, the data must be valid on the falling edge of the last cycle. 

NOWS is sampled at the midpoint of each wait cycle. If it is low, the transfer cycle terminates without further wait states. CHRDY is sampled during the first half of
the clock cycle. If it is low, further wait cycles will be inserted. 

The default for 8 bit transfers is 4 wait states. Some computers allow the number of default wait states to be changed. 

16 Bit Memory or I/O Transfer Timing Diagram (1 wait state shown)

        

An asterisk (*) denotes the point where the signal is sampled. 

[1] The portion of the address on the LA bus for the NEXT cycle may now be placed on the bus. This is used so that cards may begin decoding the address early.
Address pipelining must be active. 

[2] AEN remains low throughout the entire transfer cycle, indicating that a normal (non-DMA) transfer is occuring. 

[3] Some bus controllers sample this signal during the same clock cycle as M16, instead of during the first wait state, as shown above. In this case, IO16 needs to be
pulled low as soon as the address is decoded, which is before the I/O command lines are active. 

[4] M16 is sampled a second time, in case the adapter card did not activate the signal in time for the first sample (usually because the memory device is not
monitoring the LA bus for early address information, or is waiting for the falling edge of BALE). 

16 bit transfers follow the same basic timing as 8 bit transfers. A valid address may appear on the LA bus prior to the beginning of the transfer cycle. Unlike the SA
bus, the LA bus is not latched, and is not valid for the entire transfer cycle (on most computers). The LA bus should be latched on the falling edge of BALE. Note
that on some systems, the LA bus signals will follow the same timing as the SA bus. On either type of system, a valid address is present on the falling edge of BALE. 

I/O adapter cards do not need to monitor the LA bus or BALE, since I/O addresses are always within the address space of the SA bus. 

SBHE will be pulled low by the system board, and the adapter card must respond with IO16 or M16 at the appropriate time, or else the transfer will be split into
two seperate 8 bit transfers. Many systems expect IO16 or M16 before the command lines are valid. This requires that IO16 or M16 be pulled low as soon as the
address is decoded (before it is known whether the cycle is I/O or Memory). If the system is starting a memory cycle, it will ignore IO16 (and vice-versa for I/O
cycles and M16). 

For read operations, the data is sampled on the rising edge of the last clock cycle. For write operations, valid data appears on the bus before the end of the cycle, as
shown in the timing diagram. While the timing diagram indicates that the data needs to be sampled on the rising clock, on most systems it remains valid for the entire
clock cycle. 

The default for 16 bit transfers is 1 wait state. This may be shortened or lengthened in the same manner as 8 bit transfers, via NOWS and CHRDY. Many systems
only allow 16 bit memory devices (and not I/O devices) to transfer using 0 wait states (NOWS has no effect on 16 bit I/O cycles). 

SMRDC/SMWTC follow the same timing as MRDC/MWTC respectively when the address is within the lower 1 MB. If the address is not within the lower 1 MB
boundary, SMRDC/SMWTC will remain high during the entire cycle. 

It is also possible for an 8 bit bus cycle to use the upper portion of the bus. In this case, the timing will be similar to a 16 bit cycle, but an odd address will be present
on the bus. This means that the bus is transferring 8 bits using the upper data bits (SD8-SD15). 

Shortening or Lengthening the bus cycle:

    

An asterisk (*) denotes the point where the signal is sampled. 

W=Wait Cycle 

This timing diagram shows three different transfer cycles. The first is a 16 bit standard I/O read. This is followed by an almost identical 16 bit I/O read, with one wait
state inserted. The I/O device pulls CHRDY low to indicate that it is not ready to complete the transfer (see [1]). This inserts a wait cycle, and CHRDY is again
sampled. At this second sample, the I/O device has completed its operation and released CHRDY, and the bus cycle now terminates. 

The third cycle is an 8 bit transfer, which is shortened to 1 wait state (the default is 4) by the use of NOWS. 

I/O Port Addresses

Note: Only the first 10 address lines are decoded for I/O operations. This limits the I/O address space to address 3FF (hex) and lower. Some systems allow for 16
bit I/O address space, but may be limited due to some I/O cards only decoding 10 of these 16 bits. 

 Port (hex)
                      Port Assignments
 000-00F
          DMA Controller
 010-01F
          DMA Controller (PS/2)
 020-02F
          Master Programmable Interrupt Controller (PIC)
 030-03F
          Slave PIC
 040-05F