proc-arm926.s

自己根据lkd和情境分析

/*
 * cpu_arm926_dcache_clean_entry(addr)
 *
 * Clean the specified entry of any caches such that the MMU
 * translation fetches will obtain correct data.
 *
 * addr: cache-unaligned virtual address
 */
	.align	5
ENTRY(cpu_arm926_dcache_clean_entry)
#ifndef CONFIG_CPU_ARM926_WRITETHROUGH
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/* ================================ I-CACHE =============================== */

/*
 * cpu_arm926_icache_invalidate_range(start, end)
 *
 * This *is not* just icache.  It is to make data written to memory
 * consistent such that instructions fetched from the region are what
 * we expect.
 *
 * This is typically used after we have copied a module into kernel space,
 * and we're about to start executing code from that module.
 *
 * start: virtual start address
 * end:   virtual end address
 */
	.align	5
ENTRY(cpu_arm926_icache_invalidate_range)
	bic	r0, r0, #DCACHELINESIZE - 1	@ Safety check
	sub	r3, r1, r0
	cmp	r3, #MAX_AREA_SIZE
	bhi	cpu_arm926_cache_clean_invalidate_all_r2

1:	mcr	p15, 0, r0, c7, c5, 1		@ clean I entries
	add	r0, r0, #DCACHELINESIZE
	cmp	r0, r1
	blo	1b

	mov	r0, #0
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

ENTRY(cpu_arm926_icache_invalidate_page)
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mov	pc, lr


/* ================================== TLB ================================= */

/*
 * cpu_arm926_tlb_invalidate_all()
 *
 * Invalidate all TLB entries
 */
	.align	5
ENTRY(cpu_arm926_tlb_invalidate_all)
	mov	r0, #0
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I & D TLBs
	mov	pc, lr

/*
 * cpu_arm926_tlb_invalidate_range(start, end)
 *
 * invalidate TLB entries covering the specified range
 *
 * start: range start address
 * end:   range end address
 */
	.align	5
ENTRY(cpu_arm926_tlb_invalidate_range)
	mov	r3, #0
	mcr	p15, 0, r3, c7, c10, 4		@ drain WB

	bic	r0, r0, #(PAGESIZE - 1) & 0x00ff
	bic	r0, r0, #(PAGESIZE - 1) & 0xff00

1:	mcr	p15, 0, r0, c8, c6, 1		@ invalidate D TLB entry
	mcr	p15, 0, r0, c8, c5, 1		@ invalidate I TLB entry
	add	r0, r0, #PAGESIZE
	cmp	r0, r1
	blo	1b
	mov	pc, lr

/*
 * cpu_arm926_tlb_invalidate_page(page, flags)
 *
 * invalidate the TLB entries for the specified page.
 *
 * page:  page to invalidate
 * flags: non-zero if we include the I TLB
 */
	.align	5
ENTRY(cpu_arm926_tlb_invalidate_page)
	mov	r3, #0
	mcr	p15, 0, r3, c7, c10, 4		@ drain WB
	teq	r1, #0
	mcr	p15, 0, r0, c8, c6, 1		@ invalidate D TLB entry
	mcrne	p15, 0, r0, c8, c5, 1		@ invalidate I TLB entry
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_arm926_set_pgd(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_arm926_set_pgd)
	mov	ip, #0
#ifdef CONFIG_CPU_ARM926_WRITETHROUGH
	/* Any reason why we don't use mcr p15, 0, r0, c7, c7, 0 here? --rmk */
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
@ && 'Clean & Invalidate whole DCache'
1:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate
	bne	1b
#endif
	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
	mov	pc, lr

/*
 * cpu_arm926_set_pmd(pmdp, pmd)
 *
 * Set a level 1 translation table entry, and clean it out of
 * any caches such that the MMUs can load it correctly.
 *
 * pmdp: pointer to PMD entry
 * pmd:  PMD value to store
 */
	.align	5
ENTRY(cpu_arm926_set_pmd)
#ifdef CONFIG_CPU_ARM926_WRITETHROUGH
	eor	r2, r1, #0x0a			@ C & Section
	tst	r2, #0x0b
	biceq	r1, r1, #4			@ clear bufferable bit
#endif
	str	r1, [r0]
#ifndef CONFIG_CPU_ARM926_WRITETHROUGH
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 * cpu_arm926_set_pte(ptep, pte)
 *
 * Set a PTE and flush it out
 */
	.align	5
ENTRY(cpu_arm926_set_pte)
	str	r1, [r0], #-1024		@ linux version

	eor	r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY

	bic	r2, r1, #0xff0
	bic	r2, r2, #3
	orr	r2, r2, #HPTE_TYPE_SMALL

	tst	r1, #LPTE_USER | LPTE_EXEC	@ User or Exec?
	orrne	r2, r2, #HPTE_AP_READ

	tst	r1, #LPTE_WRITE | LPTE_DIRTY	@ Write and Dirty?
	orreq	r2, r2, #HPTE_AP_WRITE

	tst	r1, #LPTE_PRESENT | LPTE_YOUNG	@ Present and Young?
	movne	r2, #0

#ifdef CONFIG_CPU_ARM926_WRITETHROUGH
	eor	r3, r2, #0x0a			@ C & small page?
	tst	r3, #0x0b
	biceq	r2, r2, #4
#endif
	str	r2, [r0]			@ hardware version
	mov	r0, r0
#ifndef CONFIG_CPU_ARM926_WRITETHROUGH
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr


cpu_manu_name:
	.asciz	"ARM"
ENTRY(cpu_arm926_name)
	.ascii	"ARM926EJ-S"
#if defined(CONFIG_CPU_ARM926_CPU_IDLE)
	.ascii	"s"
#endif
#if defined(CONFIG_CPU_ARM926_I_CACHE_ON)
	.ascii	"i"
#endif
#if defined(CONFIG_CPU_ARM926_D_CACHE_ON)
	.ascii	"d"
#if defined(CONFIG_CPU_ARM926_WRITETHROUGH)
	.ascii	"(wt)"
#else
	.ascii	"(wb)"
#endif
#ifdef CONFIG_CPU_ARM926_ROUND_ROBIN
	.ascii	"RR"
#endif
#endif
	.ascii	"\0"
	.align

	.section ".text.init", #alloc, #execinstr

__arm926_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
	mcr	p15, 0, r4, c2, c0		@ load page table pointer


#if defined(CONFIG_CPU_ARM926_WRITETHROUGH) 
	mov	r0, #4				@ disable write-back on caches explicitly
	mcr	p15, 7, r0, c15, c0, 0
#endif 

	mov	r0, #0x1f			@ Domains 0, 1 = client
	mcr	p15, 0, r0, c3, c0		@ load domain access register
	mrc	p15, 0, r0, c1, c0		@ get control register v4
/*
 * Clear out 'unwanted' bits (then put them in if we need them)
 */
						@   VI ZFRS BLDP WCAM
	bic	r0, r0, #0x0e00
	bic	r0, r0, #0x0002
	bic	r0, r0, #0x000c
	bic	r0, r0, #0x1000 		@ ...0 000. .... 000.
/*
 * Turn on what we want
 */
	orr	r0, r0, #0x0031
	orr	r0, r0, #0x2100 		@ ..1. ...1 ..11 ...1

#ifdef CONFIG_CPU_ARM926_ROUND_ROBIN
	orr	r0, r0, #0x4000 		@ .1.. .... .... ....
#endif
#ifdef CONFIG_CPU_ARM926_D_CACHE_ON
	orr	r0, r0, #0x0004 		@ .... .... .... .1..
#endif
#ifdef CONFIG_CPU_ARM926_I_CACHE_ON
	orr	r0, r0, #0x1000 		@ ...1 .... .... ....
#endif
	mov	pc, lr

	.text

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */
	.type	arm926_processor_functions, #object
arm926_processor_functions:
	.word	cpu_arm926_data_abort
	.word	cpu_arm926_check_bugs
	.word	cpu_arm926_proc_init
	.word	cpu_arm926_proc_fin
	.word	cpu_arm926_reset
	.word	cpu_arm926_do_idle

	/* cache */
	.word	cpu_arm926_cache_clean_invalidate_all
	.word	cpu_arm926_cache_clean_invalidate_range
	.word	cpu_arm926_flush_ram_page

	/* dcache */
	.word	cpu_arm926_dcache_invalidate_range
	.word	cpu_arm926_dcache_clean_range
	.word	cpu_arm926_dcache_clean_page
	.word	cpu_arm926_dcache_clean_entry

	/* icache */
	.word	cpu_arm926_icache_invalidate_range
	.word	cpu_arm926_icache_invalidate_page

	/* tlb */
	.word	cpu_arm926_tlb_invalidate_all
	.word	cpu_arm926_tlb_invalidate_range
	.word	cpu_arm926_tlb_invalidate_page

	/* pgtable */
	.word	cpu_arm926_set_pgd
	.word	cpu_arm926_set_pmd
	.word	cpu_arm926_set_pte
	.size	arm926_processor_functions, . - arm926_processor_functions

	.type	cpu_arm926_info, #object
cpu_arm926_info:
	.long	cpu_manu_name
	.long	cpu_arm926_name
	.size	cpu_arm926_info, . - cpu_arm926_info

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv5EJ"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v5EJ"
	.size	cpu_elf_name, . - cpu_elf_name
	.align

	.section ".proc.info", #alloc, #execinstr

	.type	__arm926_proc_info,#object
__arm926_proc_info:
	.long	0x41009260
	.long	0xff00fff0
	.long	0x00000c1e			@ mmuflags
	b	__arm926_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT
	.long	cpu_arm926_info
	.long	arm926_processor_functions
	.size	__arm926_proc_info, . - __arm926_proc_info