initport.c

S3C2410学习的基础资料 大部分实验源码及工程

#define		GPH9		2	// 00 = Input 01 = Output	10 = CLKOUT0 11 = Reserved
#define		GPH8		2	// 00 = Input 01 = Output	10 = UCLK 11 = Reserved
#define		GPH7		3	// 00 = Input 01 = Output	10 = RXD2 11 = nCTS1
#define		GPH6		3	// 00 = Input 01 = Output	10 = TXD2 11 = nRTS1
#define		GPH5		2	// 00 = Input 01 = Output	10 = RXD1 11 = Reserved
#define		GPH4		2	// 00 = Input 01 = Output	10 = TXD1 11 = Reserved
#define		GPH3		2	// 00 = Input 01 = Output	10 = RXD0 11 = reserved
#define		GPH2		2	// 00 = Input 01 = Output	10 = TXD0 11 = Reserved
#define		GPH1		2	// 00 = Input 01 = Output	10 = nRTS0 11 = Reserved
#define		GPH0		2	// 00 = Input 01 = Output	10 = nCTS0 11 = Reserved
	rGPHCON = (GPH10<<20)+(GPH9<<18)+(GPH8<<16)+ \
			(GPH7<<14)+(GPH6<<12)+(GPH5<<10)+(GPH4<<8)+(GPH3<<6)+(GPH2<<4)+(GPH1<<2)+(GPH0<<0);
	rGPHUP  = 0x000007ff;    // The pull up function is disabled GPH[10:0]

// MISCELLANEOUS CONTROL REGISTER
#define		nEN_SCKE	0	// 0: SCKE = Normal 1: SCKE = L level Used to protect SDRAM during the Power_OFF moe.
#define		nEN_SCLK1	0	// 0: SCLK1= SCLK 1: SCLK1= L level Used to protect SDRAM during the Power_OFF moe.
#define		nEN_SCLK0	0	// 0: SCLK0= SCLK 1: SCLK0= L level Used to protect SDRAM during the Power_OFF moe.
#define		nRSTCON		1	// RSTOUT software control(SW_RESET) 0: nRSTOUT = 0, 1: nRSTOUT = 1.
#define		USBSUSPND1	0	// [13] USB Port 1 mode 0 = Normal 1= Suspend
#define		USBSUSPND0	0	// [12] USB Port 0 mode 0 = Normal 1= Suspend
#define		CLKSEL1		3	// CLKOUT1 output singnal source 
							// 000 = MPLL CLK 001 = UPLL CLK 010 = FCLK
							// 011 = HCLK 100 = PCLK 101 = DCLK1
							// 11x = Reserved
#define		CLKSEL0		3	// CLKOUT0 output singnal source
							// 000 = MPLL CLK 001 = UPLL CLK 010 = FCLK
							// 011 = HCLK 100 = PCLK 101 = DCLK0
							// 11x = Reserved
#define		USBPAD		0	// 0 = Use pads related USB for USB device 1 = Use pads related USB for USB host
#define		MEM_HZ_CON	0	// This bit is recommended to be 0. nGCS[7:0], nWE, nOE, nBE[3:0], nSRAS,
							//	nSCAS, ADDR[26:0] are affected during CLKCON[0] = 1.0 = Hi-Z 1 = Previous state
#define		SPUCR_L		0	// DATA[15:0] port pull-up resister  0 = Enabled 1 = Disabled
#define		SPUCR_H		0	// DATA[31:16] port pull-up resister 0 = Enabled 1 = Disabled
	rMISCCR = (nEN_SCKE<<19)+(nEN_SCLK1<<18)+(nEN_SCLK0<<17)+(nRSTCON<<16)+ \
			(USBSUSPND1<<13)+(USBSUSPND0<<12)+(CLKSEL1<<8)+(CLKSEL0<<4)+(USBPAD<<3)+(MEM_HZ_CON<<2)+(SPUCR_L<<1)+(SPUCR_H<<0);

// DCLK CONTROL REGISTERS
#define		DCLK1CMP	0	// DCLK1 Compare value clock toggle value. ( < DCLK1DIV )
							// If the DCLK1DIV is n, Low level duration is ( n + 1 ).
							// High level duration is ( (DCLK1DIV + 1) – ( n +1 ) ).
#define		DCLK1DIV	0	// DCLK1 Divide value DCLK1 frequency = source clock / ( DCLK1DIV + 1 )
#define		DCLK1SelCK	0	// Select DCLK1 source clock 0 = PCLK 1 = UCLK ( USB )
#define		DCLK1EN		0	// DCLK1 Enable 0 = Disable 1 = Enable
#define		DCLK0CMP	0	// DCLK0 Compare value clock toggle value. ( < DCLK0DIV )
							// If the DCLK0DIV is n, Low level duration is ( n + 1 ).
							// High level duration is ( (DCLK0DIV + 1) – ( n +1 ) ).
#define		DCLK0DIV	0	// DCLK0 Divide value. DCLK0 frequency = source clock / ( DCLK0DIV + 1 )
#define		DCLK0SelCK	0	// Select DCLK0 source clock 0 = PCLK 1 = UCLK ( USB )
#define		DCLK0EN		0	// DCLK0 Enable 0 = Disable 1 = Enable
	rDCLKCON = (DCLK1CMP<<24)+(DCLK1DIV<<20)+(DCLK1SelCK<<17)+(DCLK1EN<<16)+(DCLK0CMP<<8)+(DCLK0DIV<<4)+(DCLK0SelCK<<1)+(DCLK0EN<<0);

// External interrupt control register 0
#define		EINT7		2	// Set the signaling method of the EINT7.
							// 000 = Low level 001 = High level 01x = Falling edge triggered
							// 10x = Rising edge triggered 11x = Both edge triggered
#define		EINT6		2	// Set the signaling method of the EINT6.
#define		EINT5		2	// Set the signaling method of the EINT5.
#define		EINT4		2	// Set the signaling method of the EINT4.
#define		EINT3		2	// Set the signaling method of the EINT3.
#define		EINT2		2	// Set the signaling method of the EINT2.
#define		EINT1		2	// Set the signaling method of the EINT1.
#define		EINT0		2	// Set the signaling method of the EINT0.
	rEXTINT0 = (EINT7<<28)+(EINT6<<24)+(EINT5<<20)+(EINT4<<16)+(EINT3<<12)+(EINT2<<8)+(EINT1<<4)+(EINT0<<0);

// External interrupt control register 1
#define		EINT15		2	// Set the signaling method of the EINT15.
							// 000 = Low level 001 = High level 01x = Falling edge triggered
							// 10x = Rising edge triggered 11x = Both edge triggered
#define		EINT14		2	// Set the signaling method of the EINT14.
#define		EINT13		2	// Set the signaling method of the EINT13.
#define		EINT12		2	// Set the signaling method of the EINT12.
#define		EINT11		2	// Set the signaling method of the EINT11.
#define		EINT10		2	// Set the signaling method of the EINT10.
#define		EINT9		2	// Set the signaling method of the EINT9.
#define		EINT8		2	// Set the signaling method of the EINT8.
	rEXTINT1 = (EINT15<<28)+(EINT14<<24)+(EINT13<<20)+(EINT12<<16)+(EINT11<<12)+(EINT10<<8)+(EINT9<<4)+(EINT8<<0);

// External interrupt control register 2
#define		FLTEN23		0	// Filter Enable for EINT23 0 = Disable 1= Enable
#define		EINT23		2	// Set the signaling method of the EINT23.
							// 000 = Low level 001 = High level 01x = Falling edge triggered
							// 10x = Rising edge triggered 11x = Both edge triggered
#define		FLTEN22		0	// Filter Enable for EINT22 0 = Disable 1= Enable
#define		EINT22		2	// Set the signaling method of the EINT22.
#define		FLTEN21		0	// Filter Enable for EINT21
#define		EINT21		2	// Set the signaling method of the EINT21
#define		FLTEN20		0	// Filter Enable for EINT20
#define		EINT20		2	// Set the signaling method of the EINT20.
#define		FLTEN19		0	// Filter Enable for EINT19
#define		EINT19		2	// Set the signaling method of the EINT19.
#define		FLTEN18		0	// Filter Enable for EINT18
#define		EINT18		2	// Set the signaling method of the EINT18.
#define		FLTEN17		0	// Filter Enable for EINT17
#define		EINT17		2	// Set the signaling method of the EINT17.
#define		FLTEN16		0	// Filter Enable for EINT16
#define		EINT16		2	// Set the signaling method of the EINT16.
	rEXTINT2 = (FLTEN23<<31)+(EINT23<<28)+(FLTEN22<<27)+ \
				(EINT22<<24)+(FLTEN21<<23)+(EINT21<<20)+(FLTEN20<<19)+(EINT20<<16)+ \
				(FLTEN19<<15)+(EINT19<<12)+(FLTEN18<<11)+(EINT18<<8)+(FLTEN17<<7)+ \
				(EINT17<<4)+(FLTEN16<<3)+(EINT16<<0);

// EXTERNAL INTERRUPT FILTER REGISTER2
#define		FLTCLK19	0	// Filter clock of EINT19 0 = PCLK 1= EXTCLK/OSC_CLK (Selected by OM pin)
#define		EINTFLT19	0	// Filter width of EINT19
#define		FLTCLK18	0	// Filter clock of EINT18 0 = PCLK 1= EXTCLK/OSC_CLK (Selected by OM pin)
#define		EINTFLT18	0	// Filter width of EINT18
#define		FLTCLK17	0	// Filter clock of EINT17 0 = PCLK 1= EXTCLK/OSC_CLK (Selected by OM pin)
#define		EINTFLT17	0	// Filter width of EINT17
#define		FLTCLK16	0	// Filter clock of EINT16 0 = PCLK 1= EXTCLK/OSC_CLK (Selected by OM pin)
#define		EINTFLT16	0	// Filter width of EINT16
	rEINTFLT2 = (FLTCLK19<<31)+(EINTFLT19<<24)+(FLTCLK18<<23)+(EINTFLT18<<16)+(FLTCLK17<<15)+ \
			(EINTFLT17<<8)+(FLTCLK16<<7)+(EINTFLT16<<0);

// EXTERNAL INTERRUPT FILTER REGISTER3
#define		FLTCLK23	0	// Filter clock of EINT23 0 = PCLK 1= EXTCLK/OSC_CLK (Selected by OM pin)
#define		EINTFLT23	0	// Filter width of EINT23
#define		FLTCLK22	0	// Filter clock of EINT22 0 = PCLK 1= EXTCLK/OSC_CLK (Selected by OM pin)
#define		EINTFLT22	0	// Filter width of EINT22
#define		FLTCLK21	0	// Filter clock of EINT21 0 = PCLK 1= EXTCLK/OSC_CLK (Selected by OM pin)
#define		EINTFLT21	0	// Filter width of EINT21
#define		FLTCLK20	0	// Filter clock of EINT20 0 = PCLK 1= EXTCLK/OSC_CLK (Selected by OM pin)
#define		EINTFLT20	0	// Filter width of EINT20
	rEINTFLT3 = (FLTCLK23<<31)+(EINTFLT23<<24)+(FLTCLK22<<23)+(EINTFLT22<<16)+(FLTCLK21<<15)+ \
			(EINTFLT21<<8)+(FLTCLK20<<7)+(EINTFLT20<<0);

// EXTERNAL INTERRUPT MASK REGISTER (EINTMASK) 
// Interrupt mask register for 20 external interrupts (EINT[23:4]).
#define		mEINT23		1	// 0 = Enable Interrupt 1= Masked
#define		mEINT22		1	// 
#define		mEINT21		1	// 
#define		mEINT20		1	// 
#define		mEINT19		1	// 
#define		mEINT18		1	// 
#define		mEINT17		1	// 
#define		mEINT16		1	// 
#define		mEINT15		1	// 
#define		mEINT14		1	// 
#define		mEINT13		1	// 
#define		mEINT12		1	// 
#define		mEINT11		1	// 
#define		mEINT10		1	// 
#define		mEINT9		1	// 
#define		mEINT8		1	// 
#define		mEINT7		1	// 
#define		mEINT6		1	// 
#define		mEINT5		1	// 
#define		mEINT4		1	// 
	rEINTMASK = (mEINT23<<23)+(mEINT22<<22)+(mEINT21<<21)+(mEINT20<<20)+(mEINT19<<19)+(mEINT18<<18)+(mEINT17<<17)+(mEINT16<<16)+ \
			(mEINT15<<15)+(mEINT14<<14)+(mEINT13<<13)+(mEINT12<<12)+(mEINT11<<11)+(mEINT10<<10)+(mEINT9<<9)+ \
			(mEINT8<<8)+(mEINT7<<7)+(mEINT6<<6)+(mEINT5<<5)+(mEINT4<<4);

// EXTERNAL INTERRUPT PENDING REGISTER (EINTPENDn)
	rEINTPEND = 0x00fffff0;	// 清除所有悬挂.
}

/*
********************************************************************************************************
* End.
********************************************************************************************************
*/