📄 int_defs.s
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;/*************************************************************************/
;/* */
;/* Copyright Mentor Graphics Corporation 2002 */
;/* All Rights Reserved. */
;/* */
;/* THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS */
;/* THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS */
;/* SUBJECT TO LICENSE TERMS. */
;/* */
;/*************************************************************************/
;
;/*************************************************************************/
;/* */
;/* FILE NAME VERSION */
;/* */
;/* int_defs.s Nucleus PLUS\ARM PID\ADS 1.13.24 */
;/* */
;/* COMPONENT */
;/* */
;/* IN - Initialization */
;/* */
;/* DESCRIPTION */
;/* */
;/* This file contains the target processor dependent initialization */
;/* values used in int_pid.s, tct.s, and tmt.s */
;/* */
;/* DATA STRUCTURES */
;/* */
;/* NONE */
;/* */
;/* FUNCTIONS */
;/* */
;/* NONE */
;/* */
;/* DEPENDENCIES */
;/* */
;/* NONE */
;/* */
;/* HISTORY */
;/* */
;/* NAME DATE REMARKS */
;/* */
;/* B. Whatley 01-25-2001 Created the initial file for this*/
;/* port, release 1.13.20 */
;/* */
;/* D. Driscoll 05-17-2001 Updated for release 1.13.21, */
;/* Fixed 1070. */
;/* C. Sheppard 10-15-2001 Released version 1.13.22 */
;/* J. Pregeant 04-17-2002 Released version 1.13.23 */
;/* J. Pregeant 08-16-2002 Released version 1.13.24 */
;/*************************************************************************/
;/* Define constants used in low-level initialization. */
;
;/************************************/
;/* MODE BITS/MASKS DEFINES */
;/************************************/
LOCKOUT EQU &C0 ; Interrupt lockout value
LOCK_MSK EQU &C0 ; Interrupt lockout mask value
MODE_MASK EQU &1F ; Processor Mode Mask
SUP_MODE EQU &13 ; Supervisor Mode (SVC)
IRQ_MODE EQU &12 ; Interrupt Mode (IRQ)
FIQ_MODE EQU &11 ; Fast Interrupt Mode (FIQ)
I_BIT EQU &80 ; Interrupt bit of CPSR and SPSR
F_BIT EQU &40 ; Interrupt bit of CPSR and SPSR
IBIT EQU &80 ; Interrupt bit of CPSR and SPSR
FBIT EQU &40 ; Interrupt bit of CPSR and SPSR
;/************************************/
;/* SYSTEM STACK MEMORY */
;/************************************/
IRQ_STACK_SIZE EQU 1024 ; Number of bytes in IRQ stack
; -Note that the IRQ interrupt,
; by default, is managed by
; Nucleus PLUS. Only several
; words are actually used. The
; system stack is what will
; actually be used for Nuclues
; PLUS managed IRQ interrupts.
FIQ_STACK_SIZE EQU 512 ; Number of bytes in FIQ stack.
; This value is application
; specific. By default, Nucleus
; does not manage FIQ interrupts
; and furthermore, leaves them
; enabled virtually all the time.
;/************************************/
;/* SYSTEM USER STACK MEMORY */
;/************************************/
SYSTEM_SIZE EQU 1024 ; Define the system stack size
TIMER_SIZE EQU 1024 ; Define timer HISR stack size
TIMER_PRIORITY EQU 2 ; Timer HISR priority (values from
; 0 to 2, where 0 is highest)
;/************************************/
;/* ARM7 PID SPECIAL REGISTERS */
;/************************************/
PAR_PORT_BASE EQU &0D800040 ; Define base for parl port reg
; Can be used for LED control
;/************************************/
;/* SYSTEM CLOCK */
;/************************************/
TIMER1_BASE EQU &0A800000 ; Define base for all timer1 registers
TIMER2_BASE EQU &0A800020 ; Define base for timer2 registers
TIMER_LOAD_OFFSET EQU 0x00 ; Offset for timer load register
TIMER_CNTRL_OFFSET EQU 0x08 ; Offset to timer control register
TIMER_CLEAR_OFFSET EQU 0x0C ; Offset to clear timer clear register
TIMER_VAL EQU &30d4 ; Value of 10ms timer
INT_CNTRL_BASE EQU 0x0A000000 ; Define base of all interrupt
; controller registers
;/************************************/
;/* RAM ADDRESS DEFINES */
;/************************************/
;/************************************/
;/* INTERRUPT DEFINES */
;/************************************/
;ICBASE EQU &0A000000
;ICBASE_FIQ EQU &0A000100
ICBASE EQU &01e00000
ICBASE_FIQ EQU &01e00000
;IRQ_CLEAR_OFFSET EQU &0C
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
IRQ_CLEAR_OFFSET EQU &24
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;IRQ_STATUS_REG EQU &0A000000 ; Read only
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
IRQ_STATUS_REG EQU &01E00020 ; Read only = I_ISPR
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;IRQ_ENABLE_REG EQU &0A000008 ; Write only
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
IRQ_ENABLE_REG EQU &01E0000C ; Write only =INTMSK
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;IRQ_CLEAR_REG EQU &0A00000C ; Write only
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
IRQ_CLEAR_REG EQU &01E00024 ; Write only = I_ISPC
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
FIQ_CLEAR_OFFSET EQU &010C
FIQ_STATUS_REG EQU &0A000100 ; Read only
FIQ_ENABLE_REG EQU &0A000108 ; Write only
FIQ_CLEAR_REG EQU &0A00010C ; Write only
UMON_IRQ_MASK EQU 0x100 ; Mask for UMON IRQ (serial A interrupt)
;/************************************/
;/* INTERRUPT VECTOR DEFINES */
;/************************************/
;/* Defines for the vector numbers associated with each interrupt. The vector */
;/* is determined by the bit position of the interrupt in the IRQ pending register.*/
;IRQ_APB_EXP2_VECTOR EQU 15
;IRQ_APB_EXP1_VECTOR EQU 14
;IRQ_APB_EXP0_VECTOR EQU 13
;IRQ_ASB_EXP1_VECTOR EQU 12
;IRQ_ASB_EXP0_VECTOR EQU 11
;IRQ_PARA_PORT_VECTOR EQU 10
;IRQ_SER_PORTB_VECTOR EQU 9
;IRQ_SER_PORTA_VECTOR EQU 8
;IRQ_PC_CARDB_VECTOR EQU 7
;IRQ_PC_CARDA_VECTOR EQU 6
;IRQ_TIMER_2_VECTOR EQU 5
;IRQ_TIMER_1_VECTOR EQU 4
;IRQ_DEBUG_TX_VECTOR EQU 3
;IRQ_DEBUG_RX_VECTOR EQU 2
;IRQ_PROG_VECTOR EQU 1
;IRQ_UNUSED_VECTOR EQU 0
;IRQ_EINT0_VECTOR EQU 25
;IRQ_EINT1_VECTOR EQU 24
;IRQ_EINT2_VECTOR EQU 23
;IRQ_EINT3_VECTOR EQU 22
;IRQ_EINT4567_VECTOR EQU 21
;IRQ_TICK_VECTOR EQU 20
;IRQ_ZDMA0_VECTOR EQU 19
;IRQ_ZDMA1_VECTOR EQU 18
;IRQ_BDMA0_VECTOR EQU 17
;IRQ_BDMA1_VECTOR EQU 16
;IRQ_WDT_VECTOR EQU 15
;IRQ_UERR01_VECTOR EQU 14
;IRQ_TIMER0_VECTOR EQU 13
;IRQ_TIMER1_VECTOR EQU 12
;IRQ_TIMER2_VECTOR EQU 11
;IRQ_TIMER3_VECTOR EQU 10
;IRQ_TIMER4_VECTOR EQU 9
;IRQ_TIMER5_VECTOR EQU 8
;IRQ_URXD0_VECTOR EQU 7
;IRQ_URXD1_VECTOR EQU 6
;IRQ_IIC_VECTOR EQU 5
;IRQ_SIO_VECTOR EQU 4
;IRQ_UTXD0_VECTOR EQU 3
;IRQ_UTXD1_VECTOR EQU 2
;IRQ_RTC_VECTOR EQU 1
;IRQ_ADC_VECTOR EQU 0
IRQ_ADC_VECTOR EQU 31
IRQ_RTC_VECTOR EQU 30
IRQ_SPI1_VECTOR EQU 29
IRQ_UART0_VECTOR EQU 28
IRQ_IIC_VECTOR EQU 27
IRQ_USBH_VECTOR EQU 26
IRQ_USBD_VECTOR EQU 25
IRQ_Reserved_24_VECTOR EQU 24
IRQ_UART1_VECTOR EQU 23
IRQ_SPI0_VECTOR EQU 22
IRQ_SDI_VECTOR EQU 21
IRQ_DMA3_VECTOR EQU 20
IRQ_DMA2_VECTOR EQU 19
IRQ_DMA1_VECTOR EQU 18
IRQ_DMA0_VECTOR EQU 17
IRQ_LCD_VECTOR EQU 16
IRQ_UART2_VECTOR EQU 15
IRQ_TIMER4_VECTOR EQU 14
IRQ_TIMER3_VECTOR EQU 13
IRQ_TIMER2_VECTOR EQU 12
IRQ_TIMER1_VECTOR EQU 11
IRQ_TIMER0_VECTOR EQU 10
IRQ_WDT_VECTOR EQU 9
IRQ_TICK_VECTOR EQU 8
IRQ_nBATT_FLT_VECTOR EQU 7
IRQ_Reserved_6_VECTOR EQU 6
IRQ_EINT8_23_VECTOR EQU 5
IRQ_EINT4_7_VECTOR EQU 4
IRQ_EINT3_VECTOR EQU 3
IRQ_EINT2_VECTOR EQU 2
IRQ_EINT1_VECTOR EQU 1
IRQ_EINT0_VECTOR EQU 0
;/* End of low-level initialization constants. */
;/*********************************************/
;/* TC_TCB and TC_HCB STRUCT OFFSET DEFINES */
;/*********************************************/
TC_CREATED EQU &0 ; Node for linking to created task list
TC_ID EQU &C ; Internal TCB ID
TC_NAME EQU &10 ; Task name
TC_STATUS EQU &18 ; Task status
TC_DELAYED_SUSPEND EQU &19 ; Delayed task suspension
TC_PRIORITY EQU &1A ; Task priority
TC_PREEMPTION EQU &1B ; Task preemption enable
TC_SCHEDULED EQU &1C ; Task scheduled count
TC_CUR_TIME_SLICE EQU &20 ; Current time slice
TC_STACK_START EQU &24 ; Stack starting address
TC_STACK_END EQU &28 ; Stack ending address
TC_STACK_POINTER EQU &2C ; Task stack pointer
TC_STACK_SIZE EQU &30 ; Task stack's size
TC_STACK_MINIMUM EQU &34 ; Minimum stack size
TC_CURRENT_PROTECT EQU &38 ; Current protection
TC_SAVED_STACK_PTR EQU &3C ; Previous stack pointer
TC_ACTIVE_NEXT EQU &3C ; Next activated HISR
TC_TIME_SLICE EQU &40 ; Task time slice value
TC_ACTIVATION_COUNT EQU &40 ; Activation counter
TC_HISR_ENTRY EQU &44 ; HISR entry function
TC_SU_MODE EQU &48 ; Supervisor/User mode indicator
TC_MODULE EQU &4C ; Module identifier
TC_READY_PREVIOUS EQU &4C ; Previously ready TCB
TC_READY_NEXT EQU &50 ; next and previous ptrs
TC_PRIORITY_GROUP EQU &54 ; Priority group mask bit
TC_PRIORITY_HEAD EQU &58 ; Pointer to list head
TC_SUB_PRIORITY_PTR EQU &5C ; Pointer to sub-group
TC_SUB_PRIORITY EQU &60 ; Mask of sub-group bit
TC_SAVED_STATUS EQU &61 ; Previous task status
TC_SIGNAL_ACTIVE EQU &62 ; Signal active flag
TC_TASK_ENTRY EQU &64 ; Task entry function
TC_ARGC EQU &68 ; Optional task argument
TC_ARGV EQU &6C ; Optional task argument
TC_CLEANUP EQU &70 ; Clean-up routine
TC_CLEANUP_INFO EQU &74 ; Clean-up information
TC_SUSPEND_PROTECT EQU &78 ; Protection at time of task suspension
TC_TIMER_ACTIVE EQU &7C ; Active timer flag
TC_TIMER_CONTROL EQU &80 ; Timer control block
TC_SIGNALS EQU &94 ; Current signals
TC_ENABLED_SIGNALS EQU &98 ; Enabled signals
TC_SIGNAL_HANDLER EQU &9C ; Signal handling routine.
END
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