📄 flashop_intel320_.c
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/*-----------------------------------------------------------------------------*/
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/*-----------------------------------------------------------------------------*/
/* */
/* Now that you've gotten here you are probably serious about understanding */
/* the way Adam2 uses the flash. All flash operations are contained in this */
/* module. There are 7 interfaces to this module. FWBGetBlockSize, FWBErase, */
/* FWBOpen, FWBWriteByte, and FWBClose, FWBUnLock, FWBLock. */
/* FWBGetBlockSize(base); - returns the Flash Block size for the */
/* requested region so that all users of the */
/* flash understand the blocking factor. */
/* */
/* FWBErase(base,size,verbose); - Erases from base address of size in blocks. */
/* */
/* FWBOpen(Base); - Will always be called prior to FWBWriteByte,*/
/* and is responsible for unlocking the region */
/* and preparing for flash writes. */
/* */
/* FWBWriteByte(address,data); - Is called to write data to the flash */
/* address, remember that a FWBClose will be */
/* called prior to any use of the written data.*/
/* */
/* FWBClose() - Will complete any pending flash writes to a */
/* region, and lock the flash. */
/* */
/* FWBUnLock(base,size) - Unlocks the blocks specified */
/* */
/* FWBLock(base,size) - Lock the blocks specified */
/* */
/* The use of FWBOpen, FWBWriteByte, and FWBClose allows for efficient block */
/* writes. Remember it is possible to only get One FWBWriteByte in-between a */
/* FWBOpen and a FWBClose. */
/* */
/* During the Boot process the FWBGetBlockSize is called. This block can be */
/* called at any time, and returns the size of the flash blocks for the */
/* requested region. It is possible to have different size flash blocks in */
/* different memory regions. */
/* */
/* Any time the Kernel wishes to erase a block of flash, it will call the */
/* FWBErase routine. The routine is assumed to erase in blocks. That is */
/* FWBErase(CS0_BASE,1,0); will erase the block at CS0_BASE. The same can be */
/* said for FWBErase(CS0_BASE,FWBGetBlockSize(CS0_BASE),0); So that */
/* FWBErase(CS0_BASE,FWBGetBlockSize(CS0_BASE)+1,0); and */
/* FWBErase(CS0_BASE+1,FWBGetBlockSize(CS0_BASE),0); actually erases 2 blocks.*/
/* */
/* It is important to not that the FWBXxxxx routines must always leave the */
/* flash in a read mode. Failure to do this will result in a system hang. */
/* sys_printf () is also unuasable whilest the flash in not in a read mode */
/* */
/* And last but not least, all FWB... routines return TRUE if successfull and */
/* FALSE if unsuccessfull */
/* */
/*-----------------------------------------------------------------------------*/
#include "_stdio.h"
#include "flashop.h"
#include "hw.h"
void _FlashErrorOut(char *str,int sts);
int _FWBWriteBlock(void);
int _FlashOperationComplete(bit32u adr,bit32u dat,int timeoutloops);
#define FLASH_MAX_WAIT 200
/* The following are for the Intel 28FXXXC3 Flash Chips */
#define FLASH_READ_CMD 0x00FF00FF
#define FLASH_READ_CFG_CMD 0x00900090
#define FLASH_READ_STAT_CMD 0x00700070
#define FLASH_ERROR_MASK 0x001A001A
#define FLASH_WRITE_CMD 0x00400040
#define FLASH_CLEAR_SR_CMD 0x00500050
#define FLASH_ERASE_SECTOR 0x00200020 /* CMD 1 for erasing a sector */
#define FLASH_LOCK_CMD 0x00600060
#define FLASH_UNLOCK 0x00D000D0
#define FLASH_LOCK 0x00010001
#define FLASH_COMMIT_CMD 0x00D000D0
#define FLASH_WSMS 0x00800080 /* Write state machine state */
#define INTEL_FLASH_ID 0x00890089
/*#define INTEL_FLASH_8K 0x88C088C0
#define INTEL_FLASH_16K 0x88C288C2
#define INTEL_FLASH_32K 0x88C488C4*/
#define INTEL_FLASH_8K 0x88C088C1
#define INTEL_FLASH_16K 0x88C288C3
#define INTEL_FLASH_32K 0x88C488C5
#define FLASH2_OFFSET 0x00800000
#define FLASH_SECTOR_SIZE (128*1024) /* How big is a "normal" sector */
#define FLASH_ENV_SECTOR_SIZE (16*1024) /* How big is a environment sector */
#define EPLD_FLASH_WP 0x9C800008 /* EPLD register for Flash write protect */
bit32u FWBBaseAdr = 0;
int FWBvalid = 0;
int FWBopen=FALSE;
char FWBwdata[64];
static bit32u flash_size[2] = {0,0}; /* We have at most 2 banks */
bit32u total_flash = 0;
int FWBValid(bit32u base)
{
base&=0x1fffffff;
base|=0xa0000000;
if (base < (CS0_BASE + MIN_BOOT_BLOCK_SIZE))
return(0);
if (base >= (CS0_BASE + CS0_SIZE))
return(0);
return (1);
}
/* This function returns back a 0 if failure - no valid flash detected */
int FWBGet_flash_type()
{
bit32u flash_id;
bit32u flash_type;
/* Figure out if we have the right flash chips */
MEM_WRITE(CS0_BASE,FLASH_READ_CMD);
MEM_WRITE(CS0_BASE,FLASH_READ_CFG_CMD);
flash_id = MEM_READ(CS0_BASE);
flash_type = MEM_READ(CS0_BASE+4);
MEM_WRITE(CS0_BASE,FLASH_READ_CMD);
if(flash_id != INTEL_FLASH_ID)
{
return(0); /* NOT what we expected */
}
switch(flash_type)
{
case INTEL_FLASH_8K:
flash_size[0] = 2*1024*1024;
break;
case INTEL_FLASH_16K:
flash_size[0] = 4*1024*1024;
break;
case INTEL_FLASH_32K:
flash_size[0] = 8*1024*1024;
break;
default: /* Unknown type */
return(0);
}
total_flash = flash_size[0];
/* Check if we have second bank populated */
MEM_WRITE(CS0_BASE+FLASH2_OFFSET,FLASH_READ_CMD);
MEM_WRITE(CS0_BASE+FLASH2_OFFSET,FLASH_READ_CFG_CMD);
flash_id = MEM_READ(CS0_BASE+FLASH2_OFFSET);
flash_type = MEM_READ(CS0_BASE+4+FLASH2_OFFSET);
MEM_WRITE(CS0_BASE+FLASH2_OFFSET,FLASH_READ_CMD);
/* Ok we do have some Intel flash... */
if(flash_id == INTEL_FLASH_ID)
{
switch(flash_type)
{
case INTEL_FLASH_8K:
flash_size[1] = 2*1024*1024;
break;
case INTEL_FLASH_16K:
flash_size[1] = 4*1024*1024;
break;
case INTEL_FLASH_32K:
flash_size[1] = 8*1024*1024;
break;
default: /* Unknown type */
flash_size[1] = 0;
break;
}
total_flash += flash_size[1];
}
return(total_flash);
}
int FWBUnLock(bit32u adr,bit32 size)
{
bit32u *uip,uitmp;
int sts;
uip=(bit32u *)adr;
uitmp=*uip;
MEM_WRITE(adr,FLASH_LOCK_CMD);
MEM_WRITE(adr,FLASH_UNLOCK);
sts=_FlashOperationComplete(adr,uitmp,700000*FLASH_MAX_WAIT);
_FlashErrorOut("UnLock Block",sts);
return(sts==0);
}
/*Returns TRUE for success and FALSE for failure */
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