📄 avreset.s
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/* a0 = cache size
* a1 = line size
*/
/* Get an address that will correspond to the first cache line */
li a2, KSEG0BASE
/* Calc an address that will correspond to the last cache line */
addu a3, a2, a0
subu a3, a1
# Loop through all lines, writeback and invalidating each of them
1:
MIPS32_IN
cache DCACHE_INDEX_WRITEBACK_INVALIDATE, 0(a2)
MIPS32_OUT
bne a2, a3, 1b
addu a2, a1
jr ra
nop
END( sys_wb_invalidate_dchache )
LEAF( FlushDCache )
.set noreorder
li a0, 1024*16
li a1, 16
j sys_wb_invalidate_dchache
nop
/* Subroutine returnes to caller */
END( FlushDCache )
LEAF( t_clear )
.set noreorder
move v0,zero
sub v0,v0,1
mtc0 v0, C0_COMPARE
mtc0 zero, C0_COUNT
j ra
nop
END( t_clear )
LEAF( t_get )
mfc0 v0, C0_COUNT
j ra
nop
END( t_get )
/************************************************************************
* Implementation : Static functions
************************************************************************/
SLEAF( sys_get_cp0_regs )
.set noat
MFC0( a1, C0_STATUS)
sw a1, (GDB_FR_STATUS)(a0)
sw a1, (GDB_FR_CP0_REG12)(a0)
MFC0( a1, C0_BADVADDR )
sw a1, (GDB_FR_BADVADDR)(a0)
sw a1, (GDB_FR_CP0_REG8)(a0)
MFC0( a1, C0_CAUSE )
sw a1, (GDB_FR_CAUSE)(a0)
sw a1, (GDB_FR_CP0_REG13)(a0)
MFC0( a1, C0_EPC )
sw a1, (GDB_FR_EPC)(a0)
sw a1, (GDB_FR_CP0_REG14)(a0)
mflo a1
sw a1, (GDB_FR_LO)(a0)
mfhi a1
sw a1, (GDB_FR_HI)(a0)
MFC0( a1, C0_INDEX )
sw a1, (GDB_FR_CP0_INDEX)(a0)
MFC0( a1, C0_RANDOM )
sw a1, (GDB_FR_CP0_RANDOM)(a0)
MFC0( a1, C0_ENTRYLO0 )
sw a1, (GDB_FR_CP0_ENTRYLO0)(a0)
MFC0( a1, C0_ENTRYLO1 )
sw a1, (GDB_FR_CP0_ENTRYLO1)(a0)
MFC0( a1, C0_CONTEXT )
sw a1, (GDB_FR_CP0_CONTEXT)(a0)
MFC0( a1, C0_PAGEMASK )
sw a1, (GDB_FR_CP0_PAGEMASK)(a0)
MFC0( a1, C0_WIRED )
sw a1, (GDB_FR_CP0_WIRED)(a0)
/* MFC0( a1, C0_COUNT )
sw a1, (GDB_FR_CP0_REG9)(a0) */ /* do not store count register */
MFC0( a1, C0_ENTRYHI )
sw a1, (GDB_FR_CP0_ENTRYHI)(a0)
/* MFC0( a1, C0_COMPARE )
sw a1, (GDB_FR_CP0_REG11)(a0) */ /* do not store compare register */
MFC0( a1, C0_PRID )
sw a1, (GDB_FR_CP0_PRID)(a0)
MFC0( a1, C0_ERROREPC )
sw a1, (GDB_FR_CP0_ERROREPC)(a0)
MFC0( a1, C0_CONFIG )
sw a1, (GDB_FR_CP0_CONFIG)(a0)
MFC0( a1, C0_WATCHLO )
sw a1, (GDB_FR_CP0_WATCHLO)(a0)
MFC0( a1, C0_WATCHHI )
sw a1, (GDB_FR_CP0_WATCHHI)(a0)
/* TBD : reg7 and frame_ptr in GDB structure */
.set at
jr ra
nop
END( sys_get_cp0_regs )
SLEAF( sys_set_cp0_regs )
.set noat
lw a1, (GDB_FR_BADVADDR)(a0)
MTC0( a1, C0_BADVADDR )
lw a1, (GDB_FR_CAUSE)(a0)
MTC0( a1, C0_CAUSE )
lw a1, (GDB_FR_EPC)(a0)
MTC0( a1, C0_EPC )
lw a1, (GDB_FR_LO)(a0)
mtlo a1
lw a1, (GDB_FR_HI)(a0)
mthi a1
lw a1, (GDB_FR_CP0_INDEX)(a0)
MTC0( a1, C0_INDEX )
lw a1, (GDB_FR_CP0_RANDOM)(a0)
MTC0( a1, C0_RANDOM )
lw a1, (GDB_FR_CP0_ENTRYLO0)(a0)
MTC0( a1, C0_ENTRYLO0 )
lw a1, (GDB_FR_CP0_ENTRYLO1)(a0)
MTC0( a1, C0_ENTRYLO1 )
lw a1, (GDB_FR_CP0_CONTEXT)(a0)
MTC0( a1, C0_CONTEXT )
lw a1, (GDB_FR_CP0_PAGEMASK)(a0)
MTC0( a1, C0_PAGEMASK )
lw a1, (GDB_FR_CP0_WIRED)(a0)
MTC0( a1, C0_WIRED )
/* lw a1, (GDB_FR_CP0_REG9)(a0)
MTC0( a1, C0_COUNT ) */ /* do not restore count register */
lw a1, (GDB_FR_CP0_ENTRYHI)(a0)
MTC0( a1, C0_ENTRYHI )
/* lw a1, (GDB_FR_CP0_REG11)(a0)
MTC0( a1, C0_COMPARE ) */ /* do not restore compare register */
lw a1, (GDB_FR_CP0_PRID)(a0)
MTC0( a1, C0_PRID )
lw a1, (GDB_FR_CP0_ERROREPC)(a0)
MTC0( a1, C0_ERROREPC )
lw a1, (GDB_FR_CP0_CONFIG)(a0)
MTC0( a1, C0_CONFIG )
lw a1, (GDB_FR_CP0_WATCHLO)(a0)
MTC0( a1, C0_WATCHLO )
lw a1, (GDB_FR_CP0_WATCHHI)(a0)
MTC0( a1, C0_WATCHHI )
lw a1, (GDB_FR_STATUS)(a0)
MTC0( a1, C0_STATUS )
/* TBD : reg7 and frame_ptr in GDB structure */
.set at
jr ra
nop
END( sys_set_cp0_regs )
/* a0 location of new vector, copy 4 words of exception handler there */
LEAF( copy_vector )
/* Copy ram_exception_jump code to exception vector location */
/* Calc addresses */
KSEG0A( a0) /* Destination */
la t0,ram_exception_jump /* Source */
addu t1, t0, 4*4 /* copy 4 words */
CVLP1:
/* Install new instruction */
lw v0, 0(t0)
sw v0, 0(a0)
/* Whenever an instruction has been stored to KSEG1, we must
* make sure the instruction has been flushed to physical memory
* and invalidate the corresponding I-Cache line.
*/
MIPS32_IN
cache DCACHE_ADDR_HIT_WRITEBACK, 0(a0)
MIPS32_OUT
sync
MIPS32_IN
cache ICACHE_ADDR_HIT_INVALIDATE, 0(a0)
MIPS32_OUT
/* Loop */
add t0, 4
bne t0, t1, CVLP1
add a0, 4
jr ra
nop
END( setup_vector )
.align 2
SLEAF( ram_exception_jump )
/* This code is copied to the various ram exception vector
* locations (4 words are copied)
*/
la k0, exception_entry
jr k0
nop
nop /* If LA is 2 instructions this is not needed */
END( ram_exception_jump )
SLEAF( exception_entry )
/**** Store context ****/
/* Registers */
la k1, sys_gdb_regs
sw $0, (GDB_FR_REG0)(k1)
.set noat
sw $1, (GDB_FR_REG1)(k1)
.set at
sw $2, (GDB_FR_REG2)(k1)
sw $3, (GDB_FR_REG3)(k1)
sw $4, (GDB_FR_REG4)(k1)
sw $5, (GDB_FR_REG5)(k1)
sw $6, (GDB_FR_REG6)(k1)
sw $7, (GDB_FR_REG7)(k1)
sw $8, (GDB_FR_REG8)(k1)
sw $9, (GDB_FR_REG9)(k1)
sw $10, (GDB_FR_REG10)(k1)
sw $11, (GDB_FR_REG11)(k1)
sw $12, (GDB_FR_REG12)(k1)
sw $13, (GDB_FR_REG13)(k1)
sw $14, (GDB_FR_REG14)(k1)
sw $15, (GDB_FR_REG15)(k1)
sw $16, (GDB_FR_REG16)(k1)
sw $17, (GDB_FR_REG17)(k1)
sw $18, (GDB_FR_REG18)(k1)
sw $19, (GDB_FR_REG19)(k1)
sw $20, (GDB_FR_REG20)(k1)
sw $21, (GDB_FR_REG21)(k1)
sw $22, (GDB_FR_REG22)(k1)
sw $23, (GDB_FR_REG23)(k1)
sw $24, (GDB_FR_REG24)(k1)
sw $25, (GDB_FR_REG25)(k1)
/* Not k0 and k1 = $26, $27 */
sw $28, (GDB_FR_REG28)(k1)
sw $29, (GDB_FR_REG29)(k1)
sw $30, (GDB_FR_REG30)(k1)
sw $31, (GDB_FR_REG31)(k1)
/* Fetch CP0 regs */
move a0, k1
jal sys_get_cp0_regs
nop
/* Restore gp and set sp to a temporary stack space.
* This is done because we are about to call the c function
* registered as 'sys_exception_entry'. This c function will
* also restore the context, but until then, we may need
* gp for small data and sp for local data
*/
la gp, _gp
la sp, temp_stack_end
/* Jump to shell exception function */
addiu sp, -4*4
la k0, sys_exception_entry
/* lw k0, 0(k0) */
jalr k0
nop
/* If exception handler returns, we jump to restore code */
la a0, sys_gdb_regs
b exception_exit
nop
END( exception_entry )
LEAF( exception_exit )
/* Return context and return from exception */
/* Restore cp0 registes */
jal sys_set_cp0_regs
nop
/* Restore register bank */
move k1, a0
lw $0, (GDB_FR_REG0)(k1)
.set noat
lw $1, (GDB_FR_REG1)(k1)
.set at
lw $2, (GDB_FR_REG2)(k1)
lw $3, (GDB_FR_REG3)(k1)
lw $4, (GDB_FR_REG4)(k1)
lw $5, (GDB_FR_REG5)(k1)
lw $6, (GDB_FR_REG6)(k1)
lw $7, (GDB_FR_REG7)(k1)
lw $8, (GDB_FR_REG8)(k1)
lw $9, (GDB_FR_REG9)(k1)
lw $10, (GDB_FR_REG10)(k1)
lw $11, (GDB_FR_REG11)(k1)
lw $12, (GDB_FR_REG12)(k1)
lw $13, (GDB_FR_REG13)(k1)
lw $14, (GDB_FR_REG14)(k1)
lw $15, (GDB_FR_REG15)(k1)
lw $16, (GDB_FR_REG16)(k1)
lw $17, (GDB_FR_REG17)(k1)
lw $18, (GDB_FR_REG18)(k1)
lw $19, (GDB_FR_REG19)(k1)
lw $20, (GDB_FR_REG20)(k1)
lw $21, (GDB_FR_REG21)(k1)
lw $22, (GDB_FR_REG22)(k1)
lw $23, (GDB_FR_REG23)(k1)
lw $24, (GDB_FR_REG24)(k1)
lw $25, (GDB_FR_REG25)(k1)
/* Not k0 and k1 = $26, $27 */
lw $28, (GDB_FR_REG28)(k1)
lw $29, (GDB_FR_REG29)(k1)
lw $30, (GDB_FR_REG30)(k1)
lw $31, (GDB_FR_REG31)(k1)
/* return from exception */
MIPS32_IN
eret
MIPS32_OUT
nop
END( exception_exit )
/* a0 = base address of RAM for test */
/* Uses t0, t1, t2, t3, t4, t5, ra and returns v0 */
LEAF( BasicDataTest )
.set noreorder
and a0, ~3
and a1, ~3
move t0, a0
KSEG1A( t0 )
la t1, patt
li t3, 13
move v0, zero
BDLP1: lw t4, 0(t1)
sub t3, t3, 1
sw t4, 0(t0)
sw t3, 4(t0)
lw t2, 0(t0)
xor t2, t2, t4
or v0, v0, t2
BDER: bne t3, zero, BDLP1
add t1, t1, 4
bne v0, zero, bdde
nop
jr ra
nop
bdde: j DispRange
ori t5, zero, 'D'
END( BasicDataTest )
LEAF( DispRange )
.set noreorder
move t0, zero
li t1, 1
bdde1: and t2, t1, v0
bne t2, zero, bdde2
sll t1, t1, 1
bne t1, zero, bdde1
add t0, t0, 1
bdde2: li t2, 0x80000000
li t1, 31
bdde3: and t3, t2, v0
bne t3, zero, bdde4
srl t2, t2, 1
bne t2, zero, bdde3
sub t1, t1, 1
bdde4: move t2, zero
li t4, 10
bdde5: blt t0, t4, bdde6
nop
add t2, t2, 1
sub t0, t0, t4
b bdde5
nop
bdde6: move t3, zero
bdde7: blt t1, t4, bdde8
nop
add t3, t3, 1
sub t1, t1, t4
b bdde7
nop
bdde8: or t0, 0x30 /* ???xx-xx t5, t3:t1, t2:t0 */
or t1, 0x30
or t2, 0x30
or t3, 0x30
li t4, ASCII_DISP_BASE
sb t3, (3*ASCII_DISP_OFFSET)(t4)
sb t1, (4*ASCII_DISP_OFFSET)(t4)
sb t2, (6*ASCII_DISP_OFFSET)(t4)
sb t0, (7*ASCII_DISP_OFFSET)(t4)
sb t5, (2*ASCII_DISP_OFFSET)(t4)
li t1, '-'
sb t1, (5*ASCII_DISP_OFFSET)(t4)
jr ra
nop
END( DispRange )
/* a0 = base address of RAM for test */
/* a1 = Size in bytes of RAM for test */
/* Uses t0, t1, t2, t3, t4, t5, ra and returns v0 */
LEAF( RamAddressTest )
.set noreorder
and a0, ~3
and a1, ~3
move t0, a0 /* start adr */
addu t1, a0, a1 /* end adr */
subu t1, t1, 4
loop8: sw t0, 0(t0)
bne t0, t1, loop8
addu t0, t0, 4
/* Now read it back */
move t0, a0 /* start adr */
move v0, zero
loop9: lw t2, 0(t0)
xor t2, t2, t0
or v0, v0, t2
bne t0, t1, loop9
addu t0, t0, 4
bne v0, zero, RATe
nop
jr ra
nop
RATe: j DispRange
ori t5, zero, 'A'
END( RamAddressTest )
/* a0 = base address of RAM for test */
/* a1 = Size in bytes of RAM for test */
/* Uses t0, t1, t2, t3, t4, t5, t6, ra and returns v0 */
LEAF( RamDataTest )
.set noreorder
and a0, ~3
and a1, ~3
move t6, zero
move v0, zero
DDTlo: move t0, a0
addu t1, a0, a1
subu t1, t1, 4
li t3, 13
RDTl2: la t2, patt
addu t2, t2, t6
RDTl1: lw t4, 0(t2)
sub t3, t3, 1
sw t4, 0(t0)
beq t0, t1, RDTc1
addu t0, t0, 4
bne t3, zero, RDTl1
addu t2, t2, 4
b RDTl2
li t3, 13
RDTc1: move t0, a0
addu t1, a0, a1
li t3, 13
RDTl4: la t2, patt
addu t2, t2, t6
RDTl3: lw t4, 0(t2)
lw t5, 0(t0)
sub t3, t3, 1
addu t0, t0, 4
xor t4, t4, t5
beq t0, t1, RDTc2
or v0, v0, t4
bne t3, zero, RDTl3
addu t2, t2, 4
b RDTl4
li t3, 13
RDTc2: bne v0, zero, RDTe1
li t0, (1*4)
blt t6, t0,DDTlo
addu t6, t6, 4
beq a2, zero, RDTe1
li t0, (13*4)
blt t6, t0,DDTlo
nop
RDTe1: bne v0, zero, RDTeo
nop
jr ra
nop
RDTeo: j DispRange
ori t5, zero, 'I'
END( RamDataTest )
.globl patt
patt: .word 0x55555555,0xaaaaaaaa,0x33333333,0xcccccccc
.word 0x0f0f0f0f,0xf0f0f0f0,0x00ff00ff,0xff00ff00
.word 0x0000ffff,0xffff0000,0x00000000,0xffffffff
.word 0x00000000,0x55555555,0xaaaaaaaa,0x33333333
.word 0xcccccccc,0x0f0f0f0f,0xf0f0f0f0,0x00ff00ff
.word 0xff00ff00,0x0000ffff,0xffff0000,0x00000000
.word 0xffffffff
/*----------------------------------------------------------------------*/
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