avreset.s

ADAM2 sources (modified by Oleg)

/*-----------------------------------------------------------------------------*/
/*                                                                             */
/*   Copyright (C) 1996-2003 by Texas Instruments, Inc.  All rights reserved.  */
/*   Copyright (C) 2001-2003 Telogy Networks.	    						   */
/*-----------------------------------------------------------------------------*/

#include "mips.h"
#include "gdb_stub.h"
#include "hw.h"

#ifdef MIPS32SIM
#define MIPS32_IN     .set mips3
#define MIPS32_OUT    .set mips0
#else
#define MIPS32_IN
#define MIPS32_OUT
#endif

#define JSEG1(val)\
		la	v0, val;\
                KSEG1A(v0)     ;\
		jal	v0     ;

	.globl	_start
LEAF( _reset )	
	.set	noreorder
_start:
TmpAbort:
   /*------------------------------------------------------------------------*/
   /*  The following MIPS initialization code must not be modified! It       */
   /*  conforms to the recommended procedure for bringing the MIPS           */
   /*  core to a known state following a cold-reset.                         */
   /*------------------------------------------------------------------------*/
	mtc0	zero, C0_WATCHLO	/* First thing: clear watch regs */
	mtc0	zero, C0_WATCHHI
	/*-------------------------------------------------------------------*/
	/*  Next step is to initialize the CP0 Status register:              */
	/*    - Disable software & hardware interrupts (IE-0)                */
	/*    - Select bootstrap exception vectors (BEV-1)                   */
	/*                                                                   */
	/*  Important note:                                                  */
	/*    Do not modify the ERL or EXL bits in this register! When       */
	/*    ERL-1 or EXL-1, they block various other exceptions from       */
	/*    occurring. This gives us a chance to clear these potential     */
	/*    events prior to setting these bits to 0.                       */
	/*-------------------------------------------------------------------*/
        mfc0    k0, C0_STATUS
        li      k1, ~C0_STATUS_IE_BIT
        and     k0, k1			/* IE=0 */
        li      k1, C0_STATUS_BEV_BIT
        or      k0, k1                  /* BEV=1 */
        mtc0    k0, C0_STATUS
	/*-------------------------------------------------------------------*/
	/*  Now let's clean up the CP0 Cause register:                       */
	/*    - Use special interrupt vector 0x200 (IV-1)                    */
	/*    - Clear all other fields to 0. This insures that potential     */
	/*      spurious exception or interrupt events are cleared (note     */
        /*      these potential spurious events are currently blocked        */
	/*      because ERL-1 or EXL-1 from above).                          */
	/*                                                                   */
	/*  Important note:                                                  */
	/*    None of the fields in this register have a known state after   */
	/*    reset. This is why we explicitly initialize all fields in      */
	/*    this register now.                                             */
	/*-------------------------------------------------------------------*/
        li      k0, C0_CAUSE_IV_BIT
        mtc0	k0, C0_CAUSE            /* IV=1 */
	/*-------------------------------------------------------------------*/
	/*  We've taken care of clearing any spurious exceptions or          */
	/*  interrupts from occuring. It's now safe to set up the Status     */
	/*  and Config registers to our liking, including clearing the EXL   */
	/*  and ERL bits in Status. The sys_init_mips32() function does      */
        /*  this.                                                            */
	/*-------------------------------------------------------------------*/

        JSEG1( sys_init_mips32 )
	nop
        bne	v0, zero, errorout
	nop
	/*-------------------------------------------------------------------*/
	/*  Initialize instruction and data caches. This must be done        */
	/*  prior to jumping to KSEG0 addresses.                             */
	/*-------------------------------------------------------------------*/

        JSEG1( sys_init_cache )
	nop
        bne	v0, zero, errorout
	nop
   /*------------------------------------------------------------------------*/
   /*  End of critical MIPS initialization code.                             */
   /*------------------------------------------------------------------------*/

/*Added for test caching code*/
        li	t0,0x90000000
        lw	t0, 0(t0)
/*	End of Add*/

	/* Caches have now been initialised, so shift to kseg0 */
	la	t0, 1f
	KSEG0A( t0)
	j	t0
	nop
1:
	la	v0, init_platform
	jal	v0
	nop
        bne	v0, zero, errorout
	move    s8, v1

        la	k0, _reset_continue
        j	k0
	nop

	.globl	errorout

errorout:
erroroutlp:
	b	erroroutlp
        nop

.align  9       /* to 0x200 */
        .globl  _tlb_refill
_tlb_refill:
	la	k0, exception_entry
	jr	k0
	nop

.align  7       /* to 0x280 */
        .globl  _xtlb_refill
_xtlb_refill:
	la	k0, exception_entry
	jr	k0
	nop

.align  8       /* to 0x300 */
        .globl  _cache_err
_cache_err:
	la	k0, exception_entry
	jr	k0
	nop

.align  7      /* to 0x380 */
        .globl  _eothers
_eothers:
	la	k0, exception_entry
	jr	k0
	nop


.align	10  /* to 0x0400 */
	.globl	_exception

_exception:
	mfc0	k0, C0_CAUSE 
	and	k0, C0_CAUSE_CODE_MSK
	srl	k0, C0_CAUSE_CODE_SHF
	subu	k0, C0_CAUSE_CODE_INT
	beq	k0, zero, interrupt

	la	k0, exception_entry
	jr	k0
	nop

lp1:    b       lp1
        nop

interrupt:		
	/* Interrupt : For now we simply disable interrupts and return */
	
	MFC0(   k0, C0_STATUS)
	srl	k0, 1
	sll	k0, 1		
	MTC0(	k0, C0_STATUS)
        MIPS32_IN
	eret     
        MIPS32_OUT
        nop

	.globl	Adam2Calls
.align 7
Adam2Calls:
	la	t0, Tab2
	lw	t1, 0(t0)
	bge	t2, t1, BadCall
	nop
	beq     t2, zero, SioCalls
	nop
FileCalls:
 	la	t0, Lib1a
	sll	t3, t3, 2
	add	t0, t0, t3
	lw	t0, 0(t0)
	j	t0
	nop
SioCalls:
 	la	t0, Lib0a
	sll	t3, t3, 2
	add	t0, t0, t3
	lw	t0, 0(t0)
	j	t0
	nop
BadCall:
	move	v0, zero
	jr	ra	
	nop

	.globl	_yamon_calls
.align 	8  /* to 0x0500 */
_yamon_calls:
       /* Shell table to support YAMON stuff */

        .word    TmpAbort    /* SHELL_VECTOR_ADDR + ILLEGAL_CALL */
	.word	 printstrnum  /* SHELL_VECTOR_ADDR + SHELL_FUNC_PRINT_COUNT_CODE * 16 */
	.word	 TmpAbort    /* SHELL_VECTOR_ADDR + ILLEGAL_CALL */
	.word	 TmpAbort    /* SHELL_VECTOR_ADDR + ILLEGAL_CALL */
	.word	 TmpAbort    /* SHELL_VECTOR_ADDR + ILLEGAL_CALL */
	.word	 TmpAbort    /* SHELL_VECTOR_ADDR + ILLEGAL_CALL */
	.word	 TmpAbort    /* SHELL_VECTOR_ADDR + ILLEGAL_CALL */
	.word	 TmpAbort    /* SHELL_VECTOR_ADDR + ILLEGAL_CALL */
	.word	 ExitCall    /* SHELL_VECTOR_ADDR + SHELL_FUNC_EXIT_CODE * 16 */
	.word	 TmpAbort    /* SHELL_VECTOR_ADDR + ILLEGAL_CALL */
	.word	 TmpAbort    /* SHELL_VECTOR_ADDR + ILLEGAL_CALL */
	.word	 TmpAbort    /* SHELL_VECTOR_ADDR + SHELL_FUNC_FLUSH_CODE * 16 */
	.word	 TmpAbort    /* SHELL_VECTOR_ADDR + ILLEGAL_CALL */
	.word	 printstr     /* SHELL_VECTOR_ADDR + SHELL_FUNC_PRINT_CODE * 16 */ 
	.word	 TmpAbort    /* SHELL_VECTOR_ADDR + SHELL_FUNC_REGISTER_CPU_ISR_CODE * 16 */
	.word	 TmpAbort    /* SHELL_VECTOR_ADDR + SHELL_FUNC_DEREGISTER_CPU_ISR_CODE * 16 */
	.word	 TmpAbort    /* SHELL_VECTOR_ADDR + SHELL_FUNC_REGISTER_IC_ISR_CODE * 16 */
	.word	 TmpAbort    /* SHELL_VECTOR_ADDR + SHELL_FUNC_DEREGISTER_IC_ISR_CODE * 16 */
	.word	 TmpAbort    /* SHELL_VECTOR_ADDR + SHELL_FUNC_REGISTER_ESR_CODE * 16 */
	.word	 TmpAbort    /* SHELL_VECTOR_ADDR + SHELL_FUNC_DEREGISTER_ESR_CODE * 16 */
	.word	 TmpAbort    /* SHELL_VECTOR_ADDR + SHELL_FUNC_GETCHAR_CODE * 16  */
	.word	 TmpAbort    /* SHELL_VECTOR_ADDR + SHELL_FUNC_SYSCON_READ_CODE * 16 */
	.word    TmpAbort    /* SHELL_VECTOR_ADDR + SHELL_FUNC_IO_WRITE_CODE * 16 */
	.word    TmpAbort    /* SHELL_VECTOR_ADDR + SHELL_FUNC_IO_READ_CODE * 16 */
	.word    TmpAbort    /* SHELL_VECTOR_ADDR + SHELL_FUNC_IO_CTRL_CODE * 16  */
	.word    0xffffffff

_reset_continue:

	move	a0, v1
	jal	SysMemTest	/* v0 != 0 on error */
	nop
        bne	v0, zero, erroroutlp
	nop

	la	v0, init_environment
	jal	v0
	nop

        b	errorout
	nop

/* platform memory init */

SysMemTest:
        move    t8, ra

        li      a0, EMIF_SDRAM_BASE
        jal     BasicDataTest
        nop
        bne     v0, zero, SMS_Err
		nop

        li      a0, EMIF_SDRAM_BASE
        li      a1, 0x00040000
        jal     RamAddressTest
        nop
        bne     v0, zero, SMS_Err
		nop

        li      a0, EMIF_SDRAM_BASE
        li      a1, 0x00040000
        jal     RamDataTest 
        move    a2, zero
SMS_Err:        
	jr	t8
	nop

.align 2
END( _reset )

	.comm ReturnFrame,32*4

/* Execute at a specific address */
LEAF( ExeAt )
	.set	noreorder
        move    t0, a0
        move    a0, a1
        move    a1, a2
        move    a2, a3
	la	v0, ReturnFrame
        sw	$0, (0*4)(v0)
	.set noat
        sw	$1, (1*4)(v0)
	.set at
        sw	$2, (2*4)(v0)
        sw	$3, (3*4)(v0)
        sw	$4, (4*4)(v0)
        sw	$5, (5*4)(v0)
        sw	$6, (6*4)(v0)
        sw	$7, (7*4)(v0)
        sw	$8, (8*4)(v0)
        sw	$9, (9*4)(v0)
        sw	$10, (10*4)(v0)
        sw	$11, (11*4)(v0)
        sw	$12, (12*4)(v0)
        sw	$13, (13*4)(v0)
        sw	$14, (14*4)(v0)
        sw	$15, (15*4)(v0)
        sw	$16, (16*4)(v0)
        sw	$17, (17*4)(v0)
        sw	$18, (18*4)(v0)
        sw	$19, (19*4)(v0)
        sw	$20, (20*4)(v0)
        sw	$21, (21*4)(v0)
        sw	$22, (22*4)(v0)
        sw	$23, (23*4)(v0)
        sw	$24, (24*4)(v0)
        sw	$25, (25*4)(v0)
        sw	$26, (26*4)(v0)
        sw	$27, (27*4)(v0)
        sw	$28, (28*4)(v0)
        sw	$29, (29*4)(v0)
        sw	$30, (30*4)(v0)
        sw	$31, (31*4)(v0)
	jal	t0
	nop
     
        .globl    ExitCall
ExitCall:
        la	t0, ReturnFrame
	.set	noat
        lw      $1, (1*4)(t0)    /* AT */
	.set at

        /* Return Users v0 for status */

/*        lw      $2, (2*4)(t0)  skip v0 restore*/  
        lw      $3, (3*4)(t0)
        lw      $4, (4*4)(t0)
        lw      $5, (5*4)(t0)
        lw      $6, (6*4)(t0)
        lw      $7, (7*4)(t0)
        lw      $9, (9*4)(t0)
        lw      $10, (10*4)(t0)
        lw      $11, (11*4)(t0)
        lw      $12, (12*4)(t0)
        lw      $13, (13*4)(t0)
        lw      $14, (14*4)(t0)
        lw      $15, (15*4)(t0)
        lw      $16, (16*4)(t0)
        lw      $17, (17*4)(t0)
        lw      $18, (18*4)(t0)
        lw      $19, (19*4)(t0)
        lw      $20, (20*4)(t0)
        lw      $21, (21*4)(t0)
        lw      $22, (22*4)(t0)
        lw      $23, (23*4)(t0)
        lw      $24, (24*4)(t0)
        lw      $25, (25*4)(t0)
        lw      $26, (26*4)(t0)
        lw      $27, (27*4)(t0)
        lw      $28, (28*4)(t0)
        lw      $29, (29*4)(t0)
        lw      $30, (30*4)(t0)
        lw      $31, (31*4)(t0)
        lw      $8, (8*4)(t0)
	jr	ra
	nop

END( ExeAt )
	.rdata
Tab2:   .word   2
        .word   0x00010012 /* Calculated to avoid vxWorks assembler error */ /*18+(((Lib0a-Tab2-4)/4)<<16)*/
        .word   0x00190014 /* Calculated to avoid vxWorks assembler error */ /*20+(((Lib1a-Tab2-4)/4)<<16)*/
/*        .word   4+(((Lib2a-Tab2-4)/4)<<16)*/
        


Lib0a:	.word	SioVersion,SioInit
        .word   SioOutChar,SioOutStr,SioFlush
        .word   SioInChar,SioInCharCheck
        .word   sys_printf,sys_sprintf,sys_vprintf,sys_vsprintf,ExitCall
        .word   GetInputLine,sys_getenv,sys_setenv,sys_unsetenv,sys_getienv
        .word   getmonitorinfo,BasicDataTest,RamAddressTest
		.word   RamDataTest,DispHex,DispStr,SetRefClkDiv
        .word   SetRefClkPll,GetCpuFreq
        .word   PrintfRedirect,PrintfRestore,SioTxEmpty
        .word   fixenv,GetSbusFreq,GetPbusFreq
        
Lib1a:	
#ifdef FFS_SUPPORT
		.word	FileVersion,_FileSystemInit
        .word   fopen,fseek,fread,fwrite,fclose,fgetc
        .word   rewind,ftell,fflush,feof,sys_fprintf,remove
#endif
        .word	mallocc,sys_calloc,sys_realloc,sys_free,sys_memalign,sys_memmap
#ifdef FFS_SUPPORT
		.word   GetFlashOps,GetFfsBase
#endif

LEAF( printstr )
	move	a0, a1
	j	SioOutStr
	nop
END( printstr )
LEAF( printstrnum )
	move	a0, a1
	move	a1, a2
	j	SioOutStrNum
	nop
END( printstrnum )
/*----------------------------------------------------------------------*/

/*----------------------------------------------------------------------*/

#define STATUS_MIPS32	C0_STATUS_BEV_BIT
#define CONFIG0_MIPS32	(C0_CONFIG_K0_NONCOHERENT << C0_CONFIG_K0_SHF)

LEAF( sys_init_mips32 )
	.set noreorder
	
	/* Setup STATUS and CONFIG0 registers */
	li	t0, STATUS_MIPS32
	mtc0	t0, C0_STATUS 
	li	t0, CONFIG0_MIPS32
	mtc0	t0, C0_CONFIG 

	jr	ra
	move	v0, zero	
END( sys_init_mips32 )

/*----------------------------------------------------------------------*/

LEAF( sys_init_cache )
	.set noreorder
	li	a0, 1024*16
	li	a1, 16
	move	t7, ra
	jal	sys_init_icache
	nop
	jal	sys_init_dcache
	nop
	jr	t7
	move	v0, zero
	
.align 2
END( sys_init_cache )


/* Uses a0, a1, destroys a2, a3 */
LEAF( sys_init_icache )
	.set noreorder

	/*  a0 = cache size
	 *  a1 = line  size
	 */
	
	mtc0	zero, C0_TAGLO 
	mtc0	zero, C0_TAGHI 		/* TagHi is not really used */
	
	/* Get an address that will correspond to the first cache line */
	li	a2, KSEG0BASE

	/* Calc an address that will correspond to the last cache line  */
	addu	a3, a2, a0
	subu    a3, a1

	/* Loop through all lines, invalidating each of them*/
1:	
        MIPS32_IN
	cache	ICACHE_INDEX_STORE_TAG, 0(a2)	/* clear tag    */
        MIPS32_OUT
	bne	a2, a3, 1b
	addu	a2, a1

	jr	ra
	nop

END( sys_init_icache )


/* Uses a0, a1, destroys a2, a3 */
LEAF( sys_init_dcache )
	.set noreorder

	/*  a0 = cache size
	 *  a1 = line  size
	 */
	
	mtc0	zero, C0_TAGLO 
	mtc0	zero, C0_TAGHI 		/* TagHi is not really used */
	
	/* Calc an address that will correspond to the first cache line */
	li	a2, KSEG0BASE

	/* Calc an address that will correspond to the last cache line  */
	addu	a3, a2, a0
	subu    a3, a1

	/* Loop through all lines, invalidating each of them*/
1:	
        MIPS32_IN
	cache	DCACHE_INDEX_STORE_TAG, 0(a2)	/* clear tag   */
        MIPS32_OUT
	bne	a2, a3, 1b
	addu	a2, a1

	jr	ra
	nop
	
END( sys_init_dcache )


LEAF(sys_icache_invalidate_index)

	.set noreorder
	
        MIPS32_IN
	cache	ICACHE_INDEX_INVALIDATE, 0(a0)     
        MIPS32_OUT
	
	jr ra
	nop	

END(sys_icache_invalidate_index)


/* Uses a0, a1, destroys a2, a3 */
LEAF( sys_invalidate_ichache )
	.set noreorder

	/*  a0 = cache size
	 *  a1 = line  size
	 */
		
	/* Get an address that will correspond to the first cache line */
	li	a2, KSEG0BASE

	/* Calc an address that will correspond to the last cache line  */
	addu	a3, a2, a0
	subu    a3, a1

	/* Loop through all lines, invalidating each of them*/
1:	
        MIPS32_IN
	cache	ICACHE_INDEX_INVALIDATE, 0(a2)     
        MIPS32_OUT
	bne	a2, a3, 1b
	addu	a2, a1

	jr	ra
	nop
	
END( sys_invalidate_ichache )


LEAF( FlushICache )
	.set noreorder
	li	a0, 1024*16
	li	a1, 16
	j 	sys_invalidate_ichache
	nop
        /* Subroutine returnes to caller */	

END( FlushICache )

/* Uses a0, a1, destroys a2, a3 */
LEAF( sys_wb_invalidate_dchache )
	.set noreorder