avalanche.s

ADAM2 sources (modified by Oleg)

/*-----------------------------------------------------------------------------*/
/*                                                                             */
/*   Copyright (C) 1996-2003 by Texas Instruments, Inc.  All rights reserved.  */
/*   Copyright (C) 2001-2003 Telogy Networks.	    						   */
/*-----------------------------------------------------------------------------*/

#include "mips.h"
#include "hw.h"

#define RA	t4
#ifdef ACPEP
#define USE125 /* Options USE125 or USE100 to change default speed from 100 to 125 or visa versa */
#define USE64MB /* Define this if the board in question uses the new 64 MB chip modification - valid for 125 ONLY!*/
#endif /* ACPEP */                                                             

LEAF( SetRefClkDivReg )
        .set    noreorder
        li      t1, 128              /* wait 256 clocks, SDRAM to enter self refresh! */
srcdr1: bne     t1, zero, srcdr1
        sub     t1, t1, 1
        li      t1, 0xa8610a20
        sw      a0, 0(t1)
        li      t1, 10100*(75)  /* wait 10100 uS */
srcdr2: bne     t1, zero, srcdr2
        sub     t1, t1, 1
        jr      ra 
        nop
END( SetRefClkDivReg )

LEAF( SetRefClkPllReg )
	.set	noreorder

#ifdef _AVALANCHE_

/* First see if the PLL is in ByPass */

        li      t0, KSEG1(0x08611a00)   /* Check to see if we are in Bypass mode (Bit 5) */
        lw      t1, 0(t0)
        and     t1, t1, (1<<5)
        bne     t1, zero, pll_bypass

        and     a0, a0, 0xf
        sll     a0, a0, 12
/* Set the clock to n/2 mode N has to be ODD or for even n/4! For N/1 set to 0x7FE */
#ifdef ACPEP  
#ifdef USE125
        or      a0, a0, 0xFFE 
#endif
#ifdef USE100
        or      a0, a0, 0x7FE 
#endif    
#else
        or      a0, a0, (255<<3)|0x0e
#endif /* ACPEP */

/* The input PLL frequency should be between 10-62.5 Mhz */
/* Bring up internal PLL to 2X the input,EMIF will be at least 20Mhz */

        li      t1, 128              /* wait 256 clocks, SDRAM to enter self refresh! */
srcpr0: bne     t1, zero, srcpr0
        sub     t1, t1, 1

        li      t0, KSEG1(0x08610a30)  /* Switch PLL to new multiply mode */
#if defined(AR7DB) || defined(AR7VDB) || defined(AR7RD) || defined(AR7WRD)
        bne     a1, 1, setrefclk_nomclkcr
        nop
        li      t0, KSEG1(0x08610a50)
setrefclk_nomclkcr:
#endif /* AR7DB | AR7VDB | AR7RD | AR7WRD */
        li      t1, 4
        sw      t1, 0(t0)     /* Bring PLL into DIV mode */

srcpr1: lw      t1, 0(t0)     /* Wait for DIV mode to be entered */
        and     t1, t1, 1
        bne     t1, zero, srcpr1

        li      t1, 100*(75)  /* wait 100 uS */
srcpr2: bne     t1, zero, srcpr2
        sub     t1, t1, 1

        sw      a0, 0(t0)     /* Set PLL to exprcted frequency */

srcpr3: lw      t1, 0(t0)     /* Wait for DIV mode to be exited */
        and     t1, t1, 1
        beq     t1, zero, srcpr3

pll_bypass:                  /* Wait for External PLL to lock */

        li      t1, 10100*(75)  /* wait 10100 uS */
srcpr4: bne     t1, zero, srcpr4
        sub     t1, t1, 1

#endif

	jr      ra
        nop
END( SetRefClkPllReg )


LEAF( SetCpuClkPllReg )
       .set    noreorder

#ifdef _AVALANCHE_

/* First see if the PLL is in ByPass */

        li      t0, KSEG1(0x08611a00)
        lw      t1, 0(t0)
        and     t1, t1, (1<<5)
        bne     t1, zero, pll1_bypass

        and     a0, a0, 0xf
        sll     a0, a0, 12
        or      a0, a0, (255<<3)|0x0e

/* The input PLL frequency should be between 10-62.5 Mhz */
/* Bring up internal PLL to 2X the input,EMIF will be at least 20Mhz */

        li      t1, 128              /* wait 256 clocks, SDRAM to enter self refresh! */
srcp0: bne     t1, zero, srcp0
        sub     t1, t1, 1

        li      t0, KSEG1(0x08610a50)
        li      t1, 4
        sw      t1, 0(t0)     /* Bring PLL into DIV mode */

srcp1: lw      t1, 0(t0)     /* Wait for DIV mode to be entered */
        and     t1, t1, 1
        bne     t1, zero, srcp1

        li      t1, 100*(75)  /* wait 100 uS */
srcp2: bne     t1, zero, srcp2
        sub     t1, t1, 1

        sw      a0, 0(t0)     /* Set PLL to exprcted frequency */

srcp3: lw      t1, 0(t0)     /* Wait for DIV mode to be exited */
        and     t1, t1, 1
        beq     t1, zero, srcp3

pll1_bypass:                  /* Wait for External PLL to lock */

        li      t1, 10100*(75)  /* wait 10100 uS */
srcp4: bne     t1, zero, srcp4
        sub     t1, t1, 1

#endif

       jr      ra
        nop
END( SetCpuClkPllReg )


/* init_platform is used to initialize the device base memory and memory controller */
/* Returns v0=0 for OK, and v1 as amount of SDRAM found */

LEAF( init_platform )
	.set	noreorder

	move	RA, ra

	/* Initialize the vector RAM */

	li     t0, 0x80000000
	li     t1, 0x3c1a9400
	sw     t1, 0(t0)
	li     t1, 0x275a0000
	sw     t1, 4(t0)
	li     t1, 0x03400008
	sw     t1, 8(t0)

	li     t0, 0x80000100
	li     t1, 0x3c1a9400
	sw     t1, 0(t0)
	li     t1, 0x275a0100
	sw     t1, 4(t0)
	li     t1, 0x03400008
	sw     t1, 8(t0)

	li     t0, 0x80000180
        li     t1, 0x3c1a9400
	sw     t1, 0(t0)
	li     t1, 0x275a0180
	sw     t1, 4(t0)
	li     t1, 0x03400008
	sw     t1, 8(t0)
	
	li     t0, 0x80000200
	li     t1, 0x3c1a9400
	sw     t1, 0(t0)
	li     t1, 0x275a0200
	sw     t1, 4(t0)
	li     t1, 0x03400008
	sw     t1, 8(t0)
#ifdef ACPEP
#ifdef USE125
	li		a0, 4 /* Mulitply clock by 5/2 */
#endif
#ifdef USE100
	li		a0, 1 /* Mulitply clock by 2 */
#endif
	jal    SetRefClkPllReg
	nop 
#else

#ifdef _AVALANCHE_
#if defined(AR7DB) || defined(AR7VDB) || defined(AR7RD) || defined(AR7WRD)
/* SYS: 0, MIPS: 1 */
       li     t1, KSEG1(0x08611a00)
       lw     t1, 0(t1)
       li     t0, (1 << 25)
       and    t1, t1, t0
       li     a1, 0
       beq    t1, zero, mips_sync
       nop
    li     a0, 4-1
    jal    SetRefClkPllReg
       nop
       li     a1, 1
    li     a0, 4-1
    jal    SetRefClkPllReg
       nop
mips_sync:
    li     a0, 4-1
    jal    SetRefClkPllReg
    nop
#endif /* AR7DB | AR7VDB | AR7RD | AR7WRD */
#if 0

        li     t1, KSEG1(0x08610800)   /* Determine Full/Half rate modes */
        lw     t1, 0(t1)
        li     t0, 0x40000000
        and    t1, t1, t0
        li     a0, 4-1
        bne    t1, zero, dfrs1
        nop
        li     a0, 4-1
dfrs1:
        jal    SetRefClkPllReg
        nop
#endif
#endif
#endif /* ACPEP */

	/* Hurracane memory controller init */

        /* Write to the L2 Cache controller to bypass */

        li	t0, KSEG1(0x08610880)  /* Reset L2 Cache Controller */
        sw      zero, 0(t0)  

        /* Power up device modules */

        li	t0, KSEG1(0x08610a00)  /* Power up device modules */
        sw      zero, 0(t0)  
                                
#ifdef ACPEP
/* Please refer to memory pg for information */


/* Defines for data bus width */
#else /* ACPEP */
#ifdef _AVALANCHE_
#define EMSU      1
#define EMSTROBE  26
#define EMHD      3
#define RCS5_SIZE 2
#define REFRESHR  (78*20)/10   /* Refresh rate for a 20 Mhz initial value */
#else  /* SEAD */
#define EMSU      1
#define EMSTROBE  1
#define EMHD      1
#define RCS5_SIZE 0
#define REFRESHR  (78*8)/10
#endif

#define EMTA      1
#endif /* ACPEP */
#define EM32      2
#define EM16      1
#define EM08      0
                  
#ifdef ACPEP
#ifdef USE100
	li	t0, KSEG1(0x08610804)
	li	t1, 0x40000080
	sw 	t1, 0(t0)

	li	t0, KSEG1(0x08610808)
	li	t1, 0x100A0
	sw 	t1, 0(t0)

	li	t0, KSEG1(0x0861080C)
	li	t1, 0x3D5
	sw 	t1, 0(t0)

	li	t0, KSEG1(0x08610810)
	li	t1, 0x0C614316
	sw 	t1, 0(t0)

	li	t0, KSEG1(0x08610814)
	li	t1, 0x0A855C25
	sw 	t1, 0(t0)

	li	t0, KSEG1(0x08610818)
	li	t1, 0x02041028
	sw 	t1, 0(t0)

	li	t0, KSEG1(0x0861081C)
	li	t1, 0x00100086
	sw 	t1, 0(t0)
#endif

#ifdef USE125
	li	t0, KSEG1(0x08610804)
	li	t1, 0x40000080
	sw 	t1, 0(t0)

#ifdef USE64MB
	li	t0, KSEG1(0x08610808)
	li	t1, 0x00000021
	sw 	t1, 0(t0)
#else
	li	t0, KSEG1(0x08610808)
	li	t1, 0x00002020
	sw 	t1, 0(t0)
#endif

	li	t0, KSEG1(0x0861080C)
	li	t1, 0x7AA
	sw 	t1, 0(t0)

	li	t0, KSEG1(0x08610810)
	li	t1, 0x08C2461A
	sw 	t1, 0(t0)

	li	t0, KSEG1(0x08610814)
	li	t1, 0x0A465839
	sw 	t1, 0(t0)

	li	t0, KSEG1(0x08610818)
	li	t1, 0x03061839
	sw 	t1, 0(t0)

	li	t0, KSEG1(0x0861081C)
	li	t1, 0x00200116
	sw 	t1, 0(t0)
#endif

#else  /* ACPEP */

        /* Speed up this code in flash */

	/* Bank 1 - Flash (CS0) */	
	li	t0, KSEG1(0x08610810)

        lw      t3, 0(t0)                 /* Get current boot width */

        li      t1, (EMSU<<26)|(EMSTROBE<<20)|(EMHD<<17)|(EMSU<<13)|(EMSTROBE<<7)|(EMHD<<4)|(EMTA<<2)

        and     t3, t3, 3                 /* Isolate Boot width */
        or      t1, t1, t3                /* Add in boot width */
	sw	t1, 0(t0)                 /* Set new timing */

        /* Now deal with the rest of the EMIF */

        li      t3, KSEG1(EMIF_SDRAM_BASE)     /* SDRAM base address */

        jal     mode16
	move	t0, zero

        move    a0, v0

        /* Figure out the columns in the SDRAM bank (remember that X4, X8, X16, X32 RAMS) */

	jal     CheckForWrap              /* test for  8 bits ( 256w) t0=0*/
	move	t0, zero

	bne     v0,zero, badmem           /* Modified for clarity */
        nop 
	
	jal     CheckForWrap              /* test for  9 bits ( 512w) t0=1*/
	add     t0, t0, 1

	bne     v0,zero, numcol
        nop 
	
	jal     CheckForWrap              /* test for 10 bits (1024w) t0=2*/
	add     t0, t0, 1

	bne     v0,zero, numcol	
        nop 
	
	jal     CheckForWrap              /* test for 11 bits (2048w) t0=3*/
	add     t0, t0, 1

	bne     v0,zero, numcol	
        nop 

badmem:	add     t0, t0, 1
numcol:	sub     v1, t0, 1                 /* Save off columns for now */

        /* Now fine out if we have 2 external banks */

	li      t0, 0x00000008
	jal     CheckForWrap
	nop
	beq     v0, zero, bank2
        nop
	move    t0, zero
bank2:	or      t1, t0, v1                /* Col=v1, EBanks=t0 */
        or      t1, t1, a0                /* mode 16          */
	or	t1, t1, 0x2020            /* Gen Config word by adding 4 ibanks and CL=3*/

	/* Inialize the SDRAM to the found parameters (CS1, CS2) */	

	li	t0, KSEG1(0x08610808)
	sw	t1, 0(t0)

	/* Inialize memory refresh, will be slow'd down later */

	li	t0, KSEG1(0x0861080c)
	li	t1, REFRESHR                  /* Refresh=clk freq in Mhz * 7.8 */
	sw	t1, 0(t0)
		
	/* Bank 4 - SRAM, ASCII, LED, DIP-SW, UARTs (CS3) */	

	li	t0, KSEG1(0x08610814)
        li      t1, (EMSU<<26)|(EMSTROBE<<20)|(EMHD<<17)|(EMSU<<13)|(EMSTROBE<<7)|(EMHD<<4)|(EMTA<<2)|EM32
	sw	t1, 0(t0)

	/* Bank 5 - EPROM (CS4) */
	li	t0, KSEG1(0x08610818)
        li      t1, (EMSU<<26)|(EMSTROBE<<20)|(EMHD<<17)|(EMSU<<13)|(EMSTROBE<<7)|(EMHD<<4)|(EMTA<<2)|EM08
	sw	t1, 0(t0)

	/* Bank 6 - PHYs (CS5) */
	li	t0, KSEG1(0x0861081c)
        li      t1, (EMSU<<26)|(EMSTROBE<<20)|(EMHD<<17)|(EMSU<<13)|(EMSTROBE<<7)|(EMHD<<4)|(EMTA<<2)|RCS5_SIZE
	sw	t1, 0(t0)
#endif /* ACPEP */

        /* Find out How much SDRAM we have! */

	li      t0, KSEG1(EMIF_SDRAM_BASE)  /* Base */
	li      t1, EMIF_SDRAM_MAX_SIZE/2   /* Max Size/2 */
rslp:	add     t2, t1, t0
	sw      t2, 0(t2)
	srl     t1, t1, 1
	and     t1, t1, 0xfffffffc
	bne     t1, zero, rslp
	nop
	sw      t1, 0(t0)
	li      t1, 4
rs2lp:	add     t2, t1, t0
	lw      t3, 0(t2)
	sll     t1, t1, 1
	beq     t2, t3, rs2lp
	nop
	srl     v1, t1, 1		

	jr	RA
	move	v0, zero
	
/* uses t0: mode    */
/*      t3: address */
/* Destroyes t1,t2,v0,s8,ra     */

CheckForWrap:
	li      t1, KSEG1(0x08610808)
        or      t2, t0, 0x2000       /* Add cal latency = 3 for fast systems */
        or      t2, t2, a0
	sw      t2, 0(t1)            /* Configure SDRAM controler */
        li      t1, 8             
        li      t2, 256
        sw      t3, 0(t3)            /* Set Wrap test value */
CFW1:	add     v0, t2, t3
        sw      v0, 0(v0)            /* Write to index 256, 512, etc */
        add     t2, t2, t2
        sub     t1, t1, 1
        bne     t1, zero, CFW1
        nop

	lw      s8, 0(t3)            /* Get wrap test value */
	bne     t3, s8, s1_wrap      /* Jump if memory wrapped */
        li      t1, 8             
        li      t2, 256

CFW2:	add     v0, t2, t3
        lw      s8, 0(v0)            /* Verify to index 256, 512, etc */
        bne     s8, v0, s1_wrap
        add     t2, t2, t2
        sub     t1, t1, 1
        bne     t1, zero, CFW2
        nop

	move    v0, zero             /* Indicate no wrap error */
	jr      ra
	nop 
s1_wrap:
	li      v0, 1
	jr	ra
	nop

/* uses t0: mode    */
/*      t3: address */
/* Destroys t1,t2,v0,s8,a0 */

mode16: li      t1, KSEG1(0x08610808)
        or      t2, t0, 0x2000       /* Add cal latency = 3 for fast systems */
	sw      t2, 0(t1)            /* Configure SDRAM controler */
        la      t1, patt
        li      t2, 13
        move    v0, zero
m16lp:  lw      s8, 0(t1)
        sub     t2, t2, 1
        sw      s8, 0(t3)
        sw      t2, 4(t3)
        lw      a0, 0(t3)
        xor     a0, a0, s8
        or      v0, v0, a0
        bne     t2, zero, m16lp
        add     t1, t1, 4

        li      t2, 0x0000ffff
        and     t1, v0, t2
        bne     t1, zero, m32s
        li      t2, 0xffff0000
        bne     v0, t2, m32s
        nop
        li      v0, 0x4000
        jr      ra
        nop
m32s:   jr      ra
        move    v0, zero


END ( init_platform )