cpmac.c

ADAM2 sources (modified by Oleg)

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/*																				*/
/* cpmac.c: SANGAM CPMAC driver.												*/
/*																				*/
/* Author: Nakshatra Saha <[e-mail]>									*/
/*------------------------------------------------------------------------------*/

#define BD_OFFSET     0
#define RX_BUFF_SZ    1548

#define TX_DELAY      10000
#define RX_DELAY      500000
#define TRX_MIN_DELAY 100

CpmacState    cpmac_sw_state;
u1            sys_et_addr[6];
u1            et_bcast_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
CpmacState   *cpmac_st = NULL;

void FlushICache();
void FlushDCache();

void delay(u4 units)
{
	volatile u4  ii;
	for (ii = 0; ii < units; ii++);
}

/* SBL_ERESCRUNCH: failed to malloc buffer for rx bds. */
Status cpmac_init (void)
{
	u4   ii;
    volatile unsigned int pp;

  	Move(sed_lclEthAddr, sys_et_addr, sizeof(eth_HwAddress));

	if (cpmac_st != NULL) {
#if CPMAC_DEBUG
		sys_printf("\nInit called multiple times.");
#endif
		return SBL_SUCCESS;
	}
	cpmac_st = (CpmacState *)KSEG1(&cpmac_sw_state); /* Placed in uncached */

	/* Explicitly reset and bring it out of reset, the CPMAC.
	 * NOTE: EMAC0 is reset here only.
	 */
	REG32_RMW(0xa8611600, 17, 17, 0);
	delay(1000);
	REG32_RMW(0xa8611600, 17, 17, 1);
	delay(1000);
	
	/*
	 * Zero all of TX/RX DMA state head descriptor pointer registers.
	 */
	for (ii = 0; ii < CH_MAX; ii++) {
		REG32_W(CPMAC_A_TX_DMAHDP(ii), 0);
		REG32_W(CPMAC_A_RX_DMAHDP(ii), 0);
	}
	
	/* Enable TX/RX in Control registers.
	 */
	REG32_W(CPMAC_A_TX_CTRL, 1);
	REG32_W(CPMAC_A_RX_CTRL, 1);
	
	/* 
	 * Initialize the other registers as required - MII EN should be done
	 * at the end.
	 */
	REG32_W(CPMAC_A_RXUNIS, 1);    /* initialize `only' ch 0 */
	REG32_W(CPMAC_A_RXUNIC, 0xfe);
	REG32_W(CPMAC_A_RX_BO, BD_OFFSET);
	
	/* Set the MAC address. */
	for (ii = 0; ii < CH_MAX; ii++) {
		REG32_W(CPMAC_A_MACA_LO(ii), sys_et_addr[5] + ii);
	}
	REG32_W(CPMAC_A_MACA_MED, sys_et_addr[4]);
	REG32_W(CPMAC_A_MACA_HI,  sys_et_addr[0] | (sys_et_addr[1] << 8) |
		                    (sys_et_addr[2] << 16) | (sys_et_addr[3] << 24));

	REG32_RMW(CPMAC_BASE + 0x10c, 15, 0, 0x5dc);

	/* enable broadcast */
	REG32_RMW(CPMAC_BASE + 0x100, 13, 8, 0x20);
#if CPMAC_DEBUG
	sys_printf("\nallowed pkt sz: 0x%x", REG32_R(CPMAC_BASE + 0x10c, 31, 0));
#endif
	
	/* 
	 * Initialize cpmac_st, as required, eg link_state, rx_next, et al.
	 */ 
	cpmac_st->link_state = LK_DN;
	cpmac_st->rx_next = &cpmac_st->rx[0];
	
	/* 
	 * Initialize the TX/RX buffer descriptors.
	 */
	for (ii = 0; ii < TX_BD_COUNT; ii++) {
		/* Clear only the OWNS bit for the cpmac_tx to start smoothly. */
		cpmac_st->tx[ii].ctrl_n_len = 0;
	}

	if (SBL_SUCCESS != cpmac_rx_bd_init(cpmac_st->rx)) {
		return SBL_EFAILURE;
	}

	REG32_W(CPMAC_A_MACCTRL, (CPMAC_B_MACCTRL_MII |  /*| 
							  CPMAC_B_MACCTRL_TXFC |
							  CPMAC_B_MACCTRL_RXFC | */
							  CPMAC_B_MACCTRL_DPLXM));
	/* sekhar */
    for(pp=0;pp<600000; pp++);
	
    FlushICache();
	FlushDCache();
    
#ifdef CPMAC_DEBUG
    sys_printf("PHY CLK SOURCE: %d\n", REG32_R(0xA8611A00, 21,20));
#endif


	return SBL_SUCCESS;
}

/*
 * rx_bd_head should be passed as a pointer to an array of rx bds.
 * This routine initializes the rx bds as well as sets the RX DMA HDP.
 *
 * rx_bd_head passed should be in KSEG1.
 *
 * SBL_SUCCESS: Success.
 * SBL_EFAILURE: Caller should exit.
 * SBL_ERESCRUNCH: Caller should exit.
 */

/* char rx_buf[RX_BD_COUNT*RX_BUFF_SZ + (5 * RX_BD_COUNT)];*/
char rx_buf[RX_BD_COUNT][RX_BUFF_SZ + 5];

Status cpmac_rx_bd_init(BuffDesc *rx_bd_head)
{
	u4  ii;
    char* tmp;

	if (rx_bd_head == NULL) {
		return SBL_EFAILURE;
	}
     
	for (ii = 0; ii < RX_BD_COUNT; ii++) {
		rx_bd_head[ii].next = (BuffDesc *)((ii < RX_BD_COUNT - 1) ?
									PHYS(&rx_bd_head[ii + 1]) : NULL);

	tmp = &rx_buf[ii][0];
	tmp = (char *)(((((int)tmp + 3)/4) * 4) + 2);

#ifdef CPMAC_DEBUG
    sys_printf("buf %d: %08x\n", ii, tmp);
#endif