zhuangtaiji.tan.rpt

这是一个最最常用的用vhdl写的状态机

; N/A   ; None         ; 6.900 ns   ; clr  ; z2~reg0  ; Clk      ;
; N/A   ; None         ; 6.900 ns   ; clr  ; z3~reg0  ; Clk      ;
; N/A   ; None         ; 6.900 ns   ; clr  ; z4~reg0  ; Clk      ;
; N/A   ; None         ; 6.900 ns   ; clr  ; qb       ; Clk      ;
; N/A   ; None         ; 6.900 ns   ; clr  ; qc       ; Clk      ;
; N/A   ; None         ; 6.900 ns   ; clr  ; qd       ; Clk      ;
; N/A   ; None         ; 6.200 ns   ; kb3  ; qd       ; Clk      ;
; N/A   ; None         ; 6.000 ns   ; kb2  ; State.s1 ; Clk      ;
; N/A   ; None         ; 6.000 ns   ; kb2  ; State.s2 ; Clk      ;
; N/A   ; None         ; 5.900 ns   ; kb2  ; State.s3 ; Clk      ;
; N/A   ; None         ; 5.900 ns   ; kb2  ; qd       ; Clk      ;
; N/A   ; None         ; 5.200 ns   ; clr  ; z0~reg0  ; Clk      ;
; N/A   ; None         ; 5.200 ns   ; clr  ; qa       ; Clk      ;
; N/A   ; None         ; 3.600 ns   ; kb2  ; State.s0 ; Clk      ;
; N/A   ; None         ; 3.500 ns   ; kb2  ; State.s4 ; Clk      ;
+-------+--------------+------------+------+----------+----------+


+---------------------------------------------------------------+
; tco                                                           ;
+-------+--------------+------------+---------+----+------------+
; Slack ; Required tco ; Actual tco ; From    ; To ; From Clock ;
+-------+--------------+------------+---------+----+------------+
; N/A   ; None         ; 13.900 ns  ; z4~reg0 ; z4 ; Clk        ;
; N/A   ; None         ; 13.900 ns  ; z3~reg0 ; z3 ; Clk        ;
; N/A   ; None         ; 13.100 ns  ; z2~reg0 ; z2 ; Clk        ;
; N/A   ; None         ; 13.100 ns  ; z1~reg0 ; z1 ; Clk        ;
; N/A   ; None         ; 13.100 ns  ; z0~reg0 ; z0 ; Clk        ;
+-------+--------------+------------+---------+----+------------+


+----------------------------------------------------------------------+
; th                                                                   ;
+---------------+-------------+-----------+------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To       ; To Clock ;
+---------------+-------------+-----------+------+----------+----------+
; N/A           ; None        ; 0.600 ns  ; kb2  ; State.s3 ; Clk      ;
; N/A           ; None        ; 0.600 ns  ; kb2  ; State.s4 ; Clk      ;
; N/A           ; None        ; 0.500 ns  ; kb2  ; State.s0 ; Clk      ;
; N/A           ; None        ; 0.500 ns  ; kb2  ; State.s1 ; Clk      ;
; N/A           ; None        ; 0.500 ns  ; kb2  ; State.s2 ; Clk      ;
; N/A           ; None        ; -1.100 ns ; clr  ; z0~reg0  ; Clk      ;
; N/A           ; None        ; -1.100 ns ; clr  ; qa       ; Clk      ;
; N/A           ; None        ; -1.800 ns ; kb2  ; qd       ; Clk      ;
; N/A           ; None        ; -2.100 ns ; kb3  ; qd       ; Clk      ;
; N/A           ; None        ; -2.800 ns ; clr  ; z1~reg0  ; Clk      ;
; N/A           ; None        ; -2.800 ns ; clr  ; z2~reg0  ; Clk      ;
; N/A           ; None        ; -2.800 ns ; clr  ; z3~reg0  ; Clk      ;
; N/A           ; None        ; -2.800 ns ; clr  ; z4~reg0  ; Clk      ;
; N/A           ; None        ; -2.800 ns ; clr  ; qb       ; Clk      ;
; N/A           ; None        ; -2.800 ns ; clr  ; qc       ; Clk      ;
; N/A           ; None        ; -2.800 ns ; clr  ; qd       ; Clk      ;
; N/A           ; None        ; -2.900 ns ; kb0  ; qa       ; Clk      ;
; N/A           ; None        ; -3.400 ns ; kb0  ; qb       ; Clk      ;
; N/A           ; None        ; -3.400 ns ; kb0  ; qc       ; Clk      ;
; N/A           ; None        ; -3.400 ns ; kb1  ; qa       ; Clk      ;
; N/A           ; None        ; -3.400 ns ; kb3  ; qa       ; Clk      ;
; N/A           ; None        ; -3.600 ns ; kb2  ; qa       ; Clk      ;
; N/A           ; None        ; -3.900 ns ; kb1  ; qb       ; Clk      ;
; N/A           ; None        ; -3.900 ns ; kb1  ; qc       ; Clk      ;
; N/A           ; None        ; -3.900 ns ; kb3  ; qb       ; Clk      ;
; N/A           ; None        ; -3.900 ns ; kb3  ; qc       ; Clk      ;
; N/A           ; None        ; -4.100 ns ; kb2  ; qb       ; Clk      ;
; N/A           ; None        ; -4.100 ns ; kb2  ; qc       ; Clk      ;
+---------------+-------------+-----------+------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sat Dec 20 15:38:41 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off zhuangtaiji -c zhuangtaiji
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "Clk" is an undefined clock
Info: Clock "Clk" has Internal fmax of 120.48 MHz between source register "qd" and destination register "State.s3" (period= 8.3 ns)
    Info: + Longest register to register delay is 4.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B4; Fanout = 3; REG Node = 'qd'
        Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC6_B4; Fanout = 1; COMB Node = 'Select~188'
        Info: 3: + IC(0.600 ns) + CELL(1.200 ns) = 4.700 ns; Loc. = LC2_B4; Fanout = 4; REG Node = 'State.s3'
        Info: Total cell delay = 3.500 ns ( 74.47 % )
        Info: Total interconnect delay = 1.200 ns ( 25.53 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "Clk" to destination register is 5.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 14; CLK Node = 'Clk'
            Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC2_B4; Fanout = 4; REG Node = 'State.s3'
            Info: Total cell delay = 2.800 ns ( 52.83 % )
            Info: Total interconnect delay = 2.500 ns ( 47.17 % )
        Info: - Longest clock path from clock "Clk" to source register is 5.300 ns
            Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 14; CLK Node = 'Clk'
            Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_B4; Fanout = 3; REG Node = 'qd'
            Info: Total cell delay = 2.800 ns ( 52.83 % )
            Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Micro setup delay of destination is 2.500 ns
Info: tsu for register "qb" (data pin = "kb2", clock pin = "Clk") is 8.200 ns
    Info: + Longest pin to register delay is 11.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_124; Fanout = 10; PIN Node = 'kb2'
        Info: 2: + IC(1.800 ns) + CELL(2.300 ns) = 6.900 ns; Loc. = LC1_B4; Fanout = 3; COMB Node = 'process0~88'
        Info: 3: + IC(2.400 ns) + CELL(1.700 ns) = 11.000 ns; Loc. = LC5_B5; Fanout = 3; REG Node = 'qb'
        Info: Total cell delay = 6.800 ns ( 61.82 % )
        Info: Total interconnect delay = 4.200 ns ( 38.18 % )
    Info: + Micro setup delay of destination is 2.500 ns
    Info: - Shortest clock path from clock "Clk" to destination register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 14; CLK Node = 'Clk'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC5_B5; Fanout = 3; REG Node = 'qb'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: tco from clock "Clk" to destination pin "z4" through register "z4~reg0" is 13.900 ns
    Info: + Longest clock path from clock "Clk" to source register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 14; CLK Node = 'Clk'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_B4; Fanout = 1; REG Node = 'z4~reg0'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro clock to output delay of source is 1.100 ns
    Info: + Longest register to pin delay is 7.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B4; Fanout = 1; REG Node = 'z4~reg0'
        Info: 2: + IC(2.400 ns) + CELL(5.100 ns) = 7.500 ns; Loc. = PIN_86; Fanout = 0; PIN Node = 'z4'
        Info: Total cell delay = 5.100 ns ( 68.00 % )
        Info: Total interconnect delay = 2.400 ns ( 32.00 % )
Info: th for register "State.s3" (data pin = "kb2", clock pin = "Clk") is 0.600 ns
    Info: + Longest clock path from clock "Clk" to destination register is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 14; CLK Node = 'Clk'
        Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC2_B4; Fanout = 4; REG Node = 'State.s3'
        Info: Total cell delay = 2.800 ns ( 52.83 % )
        Info: Total interconnect delay = 2.500 ns ( 47.17 % )
    Info: + Micro hold delay of destination is 1.600 ns
    Info: - Shortest pin to register delay is 6.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_124; Fanout = 10; PIN Node = 'kb2'
        Info: 2: + IC(1.800 ns) + CELL(1.700 ns) = 6.300 ns; Loc. = LC2_B4; Fanout = 4; REG Node = 'State.s3'
        Info: Total cell delay = 4.500 ns ( 71.43 % )
        Info: Total interconnect delay = 1.800 ns ( 28.57 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Dec 20 15:38:41 2008
    Info: Elapsed time: 00:00:01