zhuangtaiji.tan.qmsg

这是一个最最常用的用vhdl写的状态机

{ "Info" "ITDB_FULL_TCO_RESULT" "Clk z4 z4~reg0 13.900 ns register " "Info: tco from clock \"Clk\" to destination pin \"z4\" through register \"z4~reg0\" is 13.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 5.300 ns + Longest register " "Info: + Longest clock path from clock \"Clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns Clk 1 CLK PIN_55 14 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 14; CLK Node = 'Clk'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "" { Clk } "NODE_NAME" } "" } } { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns z4~reg0 2 REG LC8_B4 1 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_B4; Fanout = 1; REG Node = 'z4~reg0'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "2.500 ns" { Clk z4~reg0 } "NODE_NAME" } "" } } { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "5.300 ns" { Clk z4~reg0 } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { Clk Clk~out z4~reg0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.500 ns + Longest register pin " "Info: + Longest register to pin delay is 7.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns z4~reg0 1 REG LC8_B4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B4; Fanout = 1; REG Node = 'z4~reg0'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "" { z4~reg0 } "NODE_NAME" } "" } } { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(5.100 ns) 7.500 ns z4 2 PIN PIN_86 0 " "Info: 2: + IC(2.400 ns) + CELL(5.100 ns) = 7.500 ns; Loc. = PIN_86; Fanout = 0; PIN Node = 'z4'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "7.500 ns" { z4~reg0 z4 } "NODE_NAME" } "" } } { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns ( 68.00 % ) " "Info: Total cell delay = 5.100 ns ( 68.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.400 ns ( 32.00 % ) " "Info: Total interconnect delay = 2.400 ns ( 32.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "7.500 ns" { z4~reg0 z4 } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "7.500 ns" { z4~reg0 z4 } { 0.000ns 2.400ns } { 0.000ns 5.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "5.300 ns" { Clk z4~reg0 } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { Clk Clk~out z4~reg0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "7.500 ns" { z4~reg0 z4 } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "7.500 ns" { z4~reg0 z4 } { 0.000ns 2.400ns } { 0.000ns 5.100ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "State.s3 kb2 Clk 0.600 ns register " "Info: th for register \"State.s3\" (data pin = \"kb2\", clock pin = \"Clk\") is 0.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 5.300 ns + Longest register " "Info: + Longest clock path from clock \"Clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns Clk 1 CLK PIN_55 14 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 14; CLK Node = 'Clk'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "" { Clk } "NODE_NAME" } "" } } { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns State.s3 2 REG LC2_B4 4 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC2_B4; Fanout = 4; REG Node = 'State.s3'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "2.500 ns" { Clk State.s3 } "NODE_NAME" } "" } } { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "5.300 ns" { Clk State.s3 } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { Clk Clk~out State.s3 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.300 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns kb2 1 PIN PIN_124 10 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_124; Fanout = 10; PIN Node = 'kb2'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "" { kb2 } "NODE_NAME" } "" } } { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.700 ns) 6.300 ns State.s3 2 REG LC2_B4 4 " "Info: 2: + IC(1.800 ns) + CELL(1.700 ns) = 6.300 ns; Loc. = LC2_B4; Fanout = 4; REG Node = 'State.s3'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "3.500 ns" { kb2 State.s3 } "NODE_NAME" } "" } } { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns ( 71.43 % ) " "Info: Total cell delay = 4.500 ns ( 71.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns ( 28.57 % ) " "Info: Total interconnect delay = 1.800 ns ( 28.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "6.300 ns" { kb2 State.s3 } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "6.300 ns" { kb2 kb2~out State.s3 } { 0.000ns 0.000ns 1.800ns } { 0.000ns 2.800ns 1.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "5.300 ns" { Clk State.s3 } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { Clk Clk~out State.s3 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "6.300 ns" { kb2 State.s3 } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "6.300 ns" { kb2 kb2~out State.s3 } { 0.000ns 0.000ns 1.800ns } { 0.000ns 2.800ns 1.700ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Dec 20 15:38:41 2008 " "Info: Processing ended: Sat Dec 20 15:38:41 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}