zhuangtaiji.tan.qmsg

这是一个最最常用的用vhdl写的状态机

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clk " "Info: Assuming node \"Clk\" is an undefined clock" {  } { { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 8 -1 0 } } { "e:/program/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/program/quartus/bin/Assignment Editor.qase" 1 { { 0 "Clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk register qd register State.s3 120.48 MHz 8.3 ns Internal " "Info: Clock \"Clk\" has Internal fmax of 120.48 MHz between source register \"qd\" and destination register \"State.s3\" (period= 8.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.700 ns + Longest register register " "Info: + Longest register to register delay is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns qd 1 REG LC4_B4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B4; Fanout = 3; REG Node = 'qd'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "" { qd } "NODE_NAME" } "" } } { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns Select~188 2 COMB LC6_B4 1 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC6_B4; Fanout = 1; COMB Node = 'Select~188'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "2.900 ns" { qd Select~188 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 4.700 ns State.s3 3 REG LC2_B4 4 " "Info: 3: + IC(0.600 ns) + CELL(1.200 ns) = 4.700 ns; Loc. = LC2_B4; Fanout = 4; REG Node = 'State.s3'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "1.800 ns" { Select~188 State.s3 } "NODE_NAME" } "" } } { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 74.47 % ) " "Info: Total cell delay = 3.500 ns ( 74.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 25.53 % ) " "Info: Total interconnect delay = 1.200 ns ( 25.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "4.700 ns" { qd Select~188 State.s3 } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "4.700 ns" { qd Select~188 State.s3 } { 0.000ns 0.600ns 0.600ns } { 0.000ns 2.300ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"Clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns Clk 1 CLK PIN_55 14 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 14; CLK Node = 'Clk'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "" { Clk } "NODE_NAME" } "" } } { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns State.s3 2 REG LC2_B4 4 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC2_B4; Fanout = 4; REG Node = 'State.s3'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "2.500 ns" { Clk State.s3 } "NODE_NAME" } "" } } { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "5.300 ns" { Clk State.s3 } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { Clk Clk~out State.s3 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"Clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns Clk 1 CLK PIN_55 14 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 14; CLK Node = 'Clk'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "" { Clk } "NODE_NAME" } "" } } { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns qd 2 REG LC4_B4 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC4_B4; Fanout = 3; REG Node = 'qd'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "2.500 ns" { Clk qd } "NODE_NAME" } "" } } { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "5.300 ns" { Clk qd } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { Clk Clk~out qd } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "5.300 ns" { Clk State.s3 } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { Clk Clk~out State.s3 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "5.300 ns" { Clk qd } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { Clk Clk~out qd } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "4.700 ns" { qd Select~188 State.s3 } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "4.700 ns" { qd Select~188 State.s3 } { 0.000ns 0.600ns 0.600ns } { 0.000ns 2.300ns 1.200ns } } } { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "5.300 ns" { Clk State.s3 } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { Clk Clk~out State.s3 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "5.300 ns" { Clk qd } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { Clk Clk~out qd } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "qb kb2 Clk 8.200 ns register " "Info: tsu for register \"qb\" (data pin = \"kb2\", clock pin = \"Clk\") is 8.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.000 ns + Longest pin register " "Info: + Longest pin to register delay is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns kb2 1 PIN PIN_124 10 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_124; Fanout = 10; PIN Node = 'kb2'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "" { kb2 } "NODE_NAME" } "" } } { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(2.300 ns) 6.900 ns process0~88 2 COMB LC1_B4 3 " "Info: 2: + IC(1.800 ns) + CELL(2.300 ns) = 6.900 ns; Loc. = LC1_B4; Fanout = 3; COMB Node = 'process0~88'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "4.100 ns" { kb2 process0~88 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(1.700 ns) 11.000 ns qb 3 REG LC5_B5 3 " "Info: 3: + IC(2.400 ns) + CELL(1.700 ns) = 11.000 ns; Loc. = LC5_B5; Fanout = 3; REG Node = 'qb'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "4.100 ns" { process0~88 qb } "NODE_NAME" } "" } } { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.800 ns ( 61.82 % ) " "Info: Total cell delay = 6.800 ns ( 61.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.200 ns ( 38.18 % ) " "Info: Total interconnect delay = 4.200 ns ( 38.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "11.000 ns" { kb2 process0~88 qb } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "11.000 ns" { kb2 kb2~out process0~88 qb } { 0.000ns 0.000ns 1.800ns 2.400ns } { 0.000ns 2.800ns 2.300ns 1.700ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 5.300 ns - Shortest register " "Info: - Shortest clock path from clock \"Clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns Clk 1 CLK PIN_55 14 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_55; Fanout = 14; CLK Node = 'Clk'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "" { Clk } "NODE_NAME" } "" } } { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns qb 2 REG LC5_B5 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC5_B5; Fanout = 3; REG Node = 'qb'" {  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "2.500 ns" { Clk qb } "NODE_NAME" } "" } } { "zhuangtaiji.vhd" "" { Text "D:/shudian/quartus/zhuangtaiji/zhuangtaiji.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "5.300 ns" { Clk qb } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { Clk Clk~out qb } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "11.000 ns" { kb2 process0~88 qb } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "11.000 ns" { kb2 kb2~out process0~88 qb } { 0.000ns 0.000ns 1.800ns 2.400ns } { 0.000ns 2.800ns 2.300ns 1.700ns } } } { "e:/program/quartus/bin/Report_Window_01.qrpt" "" { Report "e:/program/quartus/bin/Report_Window_01.qrpt" "Compiler" "zhuangtaiji" "UNKNOWN" "V1" "D:/shudian/quartus/zhuangtaiji/db/zhuangtaiji.quartus_db" { Floorplan "D:/shudian/quartus/zhuangtaiji/" "" "5.300 ns" { Clk qb } "NODE_NAME" } "" } } { "e:/program/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { Clk Clk~out qb } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}