zhuangtaiji.vhd

这是一个最最常用的用vhdl写的状态机

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 

entity zhuangtaiji is
port(
Clk,clr:IN Std_Logic;
kb0,kb1,kb2,kb3:IN std_logic;
z0,z1,z2,z3,z4,z5:out std_logic:='0'              --z0衣量设置z1温度设置z2方式设置
);
end zhuangtaiji; 

architecture behav of zhuangtaiji is
TYPE State_Type IS (S0,S1,s2,s3,s4);
SIGNAL State : State_Type:=s0;
signal qa,qb,qc,qd:std_logic:='0';
begin
   PROCESS(clk,clr)
begin
if clr='1' then state <= s0;
elsIF Clk'EVENT AND Clk = '1' THEN
     CASE State IS
         WHEN S0 =>                                                --衣量设置
            z0<='1';z1<='0';z2<='0';z3<='0';z4<='0';qb<='0';qc<='0';qd<='0';
            IF (kb2 = '1' and qa = '1' ) then state <= s1;
            ELSif ( (kb0 /= '0' or kb1 /='0') and kb2 = '0' and kb3='0')  then qa<='1';
            else state <= s0;
            END IF;
         WHEN s1 =>                                                --温度设置
            z0<='0';z1<='1';z2<='0';z3<='0';z4<='0';qa<='0';qc<='0';qd<='0'; 
            IF (kb2 = '1' and qb = '1')  then state <= s2;
            ELSif ( (kb0 /= '0' or kb1 /='0') and kb2 = '0' and kb3='0')  then qb<= '1';
            else state <= s1;
            END IF;
         when s2 =>                                                --方式设置
            z0<='0';z1<='0';z2<='1';z3<='0';z4<='0';qb<='0';qd<='0';qa<='0'; 
            IF (kb2 = '1' and qc = '1')  then state <= s3;
            ELSif ( (kb0 /= '0' or kb1 /='0') and kb2 = '0' and kb3='0')  then qc<= '1';
            else state <= s2;
            END IF;
         when s3 =>                                                --烘干设置
            z0<='0';z1<='0';z2<='0';z3<='1';z4<='0';qb<='0';qc<='0';qa<='0'; 
            IF (kb2 = '1' and qd = '1')  then state <= s4;
            ELSif (kb2 = '0' and kb3='0')  then qd<= '1';
            else state <= s3;
            END IF;
         when s4 =>
            z0<='0';z1<='0';z2<='0';z3<='0';z4<='1';              --开始洗衣服
            qa<='0';qb<='0';qc<='0';qd<='0';


end case;
end if;
end process;
end behav;