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📄 s1eig.mdl

📁 Gives all the matlab codes for dynamic simulation of electric machinery by Chee-Mun Ong
💻 MDL
📖 第 1 页 / 共 3 页
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	      Branch {
		Points			[10, 0; 0, 25]
		DstBlock		"Mux1"
		DstPort			3
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	    }
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	  SrcBlock		  "VIPQ"
	  SrcPort		  2
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	  SrcBlock		  "VIPQ"
	  SrcPort		  3
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	  DstPort		  1
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	Line {
	  SrcBlock		  "VIPQ"
	  SrcPort		  4
	  DstBlock		  "out_Qgen"
	  DstPort		  1
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	Line {
	  SrcBlock		  "Rotor"
	  SrcPort		  1
	  Points		  [0, 0]
	  Branch {
	    Points		    [15, 0; 0, 125; -450, 0; 0, -55]
	    DstBlock		    "qde2qdr"
	    DstPort		    3
	  }
	  Branch {
	    DstBlock		    "out_delta"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Rotor"
	  SrcPort		  2
	  DstBlock		  "out_puslip"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "in_vqie"
	  SrcPort		  1
	  Points		  [35, 35]
	  DstBlock		  "qde2qdr"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "in_vdie"
	  SrcPort		  1
	  DstBlock		  "qde2qdr"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "stator_wdg"
	  SrcPort		  1
	  Points		  [10, 0; 0, -85]
	  DstBlock		  "VIPQ"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "stator_wdg"
	  SrcPort		  2
	  Points		  [30, 0; 0, -65]
	  DstBlock		  "VIPQ"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "stator_wdg"
	  SrcPort		  4
	  Points		  [0, 0]
	  Branch {
	    Points		    [95, 0; 0, -100]
	    DstBlock		    "VIPQ"
	    DstPort		    4
	  }
	  Branch {
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	    DstBlock		    "Gain2"
	    DstPort		    1
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	  Branch {
	    DstBlock		    "Rotor"
	    DstPort		    4
	  }
	}
	Line {
	  SrcBlock		  "in_Ef'"
	  SrcPort		  1
	  DstBlock		  "sum"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Rotor"
	  SrcPort		  3
	  DstBlock		  "out_Tem"
	  DstPort		  1
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	  SrcPort		  1
	  DstBlock		  "Edp"
	  DstPort		  1
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	  SrcPort		  1
	  DstBlock		  "1/Tpqo"
	  DstPort		  1
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	  SrcBlock		  "stator_wdg"
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	    DstPort		    2
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	    DstBlock		    "Gain3"
	    DstPort		    1
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	    Points		    [60, 0; 0, 5]
	    DstBlock		    "Rotor"
	    DstPort		    3
	  }
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	  SrcPort		  1
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	  DstPort		  1
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	  SrcBlock		  "Edp"
	  SrcPort		  1
	  Points		  [0, 0]
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	    DstBlock		    "sum1"
	    DstPort		    2
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	    DstBlock		    "stator_wdg"
	    DstPort		    2
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	    Points		    [190, 0; 0, -150]
	    DstBlock		    "Rotor"
	    DstPort		    2
	  }
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	  SrcBlock		  "qde2qdr"
	  SrcPort		  1
	  DstBlock		  "stator_wdg"
	  DstPort		  3
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	  SrcBlock		  "qde2qdr"
	  SrcPort		  2
	  DstBlock		  "stator_wdg"
	  DstPort		  4
	}
	Line {
	  SrcBlock		  "in_Tmech"
	  SrcPort		  1
	  DstBlock		  "Rotor"
	  DstPort		  5
	}
	Line {
	  SrcBlock		  "VIPQ"
	  SrcPort		  1
	  DstBlock		  "out_|Vt|"
	  DstPort		  1
	}
	Annotation {
	  Position		  [187, 242]
	  VerticalAlignment	  top
	  Text			  "vdir"
	}
	Annotation {
	  Position		  [77, 112]
	  VerticalAlignment	  top
	  Text			  "Ef'"
	}
	Annotation {
	  Position		  [577, 177]
	  VerticalAlignment	  top
	  Text			  "delta"
	}
	Annotation {
	  Position		  [327, 212]
	  VerticalAlignment	  top
	  Text			  "iq"
	}
	Annotation {
	  Position		  [327, 242]
	  VerticalAlignment	  top
	  Text			  "id"
	}
	Annotation {
	  Position		  [512, 67]
	  VerticalAlignment	  top
	  Text			  "|Vt|"
	}
	Annotation {
	  Position		  [557, 392]
	  VerticalAlignment	  top
	  Text			  "Fixed excitation transient model in generato"
				  "r notation"
	}
	Annotation {
	  Position		  [277, 112]
	  VerticalAlignment	  top
	  Text			  "Eqp_"
	}
	Annotation {
	  Position		  [192, 207]
	  VerticalAlignment	  top
	  Text			  "vqir"
	}
      }
    }
    Block {
      BlockType		      Outport
      Name		      "out_|Vt|"
      Position		      [335, 75, 355, 95]
      Port		      "1"
      OutputWhenDisabled      held
      InitialOutput	      "0"
    }
    Block {
      BlockType		      Outport
      Name		      "out_|igen|"
      Position		      [400, 100, 420, 120]
      Port		      "2"
      OutputWhenDisabled      held
      InitialOutput	      "0"
    }
    Block {
      BlockType		      Outport
      Name		      "out_Pgen"
      Position		      [335, 125, 355, 145]
      Port		      "3"
      OutputWhenDisabled      held
      InitialOutput	      "0"
    }
    Block {
      BlockType		      Outport
      Name		      "out_Qgen"
      Position		      [405, 150, 425, 170]
      Port		      "4"
      OutputWhenDisabled      held
      InitialOutput	      "0"
    }
    Block {
      BlockType		      Outport
      Name		      "out_delta"
      Position		      [335, 175, 355, 195]
      Port		      "5"
      OutputWhenDisabled      held
      InitialOutput	      "0"
    }
    Block {
      BlockType		      Outport
      Name		      "out_puslip"
      Position		      [405, 200, 425, 220]
      Port		      "6"
      OutputWhenDisabled      held
      InitialOutput	      "0"
    }
    Block {
      BlockType		      Outport
      Name		      "out_Tem"
      Position		      [340, 225, 360, 245]
      Port		      "7"
      OutputWhenDisabled      held
      InitialOutput	      "0"
    }
    Line {
      SrcBlock		      "tmodel"
      SrcPort		      1
      DstBlock		      "out_|Vt|"
      DstPort		      1
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    Line {
      SrcBlock		      "tmodel"
      SrcPort		      2
      DstBlock		      "out_|igen|"
      DstPort		      1
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    Line {
      SrcBlock		      "tmodel"
      SrcPort		      3
      DstBlock		      "out_Pgen"
      DstPort		      1
    }
    Line {
      SrcBlock		      "tmodel"
      SrcPort		      4
      DstBlock		      "out_Qgen"
      DstPort		      1
    }
    Line {
      SrcBlock		      "tmodel"
      SrcPort		      5
      DstBlock		      "out_delta"
      DstPort		      1
    }
    Line {
      SrcBlock		      "tmodel"
      SrcPort		      6
      DstBlock		      "out_puslip"
      DstPort		      1
    }
    Line {
      SrcBlock		      "in_Ef'"
      SrcPort		      1
      DstBlock		      "tmodel"
      DstPort		      1
    }
    Line {
      SrcBlock		      "in_vqie"
      SrcPort		      1
      DstBlock		      "tmodel"
      DstPort		      2
    }
    Line {
      SrcBlock		      "in_vdie"
      SrcPort		      1
      DstBlock		      "tmodel"
      DstPort		      3
    }
    Line {
      SrcBlock		      "in_Tmech"
      SrcPort		      1
      DstBlock		      "tmodel"
      DstPort		      4
    }
    Line {
      SrcBlock		      "tmodel"
      SrcPort		      7
      DstBlock		      "out_Tem"
      DstPort		      1
    }
  }
}

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