📄 s3geig.mdl
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Line {
SrcBlock "delta "
SrcPort 1
Points [10, 0; 0, -20]
DstBlock "Mux"
DstPort 3
}
Line {
SrcBlock "vde"
SrcPort 1
DstBlock "Mux"
DstPort 2
}
}
}
Block {
BlockType SubSystem
Name "qdr2qde"
Position [450, 369, 490, 421]
ShowPortLabels off
System {
Name "qdr2qde"
Location [52, 139, 575, 326]
Open off
ScreenColor white
Block {
BlockType Inport
Name "-iqr"
Position [15, 40, 35, 60]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "-idr"
Position [15, 80, 35, 100]
Port "2"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "delta"
Position [15, 120, 35, 140]
Port "3"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Mux
Name "Mux"
Position [75, 27, 100, 153]
ShowName off
Inputs "3"
}
Block {
BlockType Fcn
Name "fcn"
Position [155, 36, 360, 64]
Expr "u[1]*cos(u[3]) + u[2]*sin(u[3])"
}
Block {
BlockType Fcn
Name "fcn1"
Position [150, 116, 360, 144]
Expr "-u[1]*sin(u[3]) + u[2]*cos(u[3])"
}
Block {
BlockType Outport
Name "-iqe"
Position [420, 40, 440, 60]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "-ide"
Position [420, 120, 440, 140]
Port "2"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "fcn1"
SrcPort 1
DstBlock "-ide"
DstPort 1
}
Line {
SrcBlock "-iqr"
SrcPort 1
DstBlock "Mux"
DstPort 1
}
Line {
SrcBlock "fcn"
SrcPort 1
DstBlock "-iqe"
DstPort 1
}
Line {
SrcBlock "Mux"
SrcPort 1
Points [0, 0]
Branch {
Points [20, 0; 0, -40]
DstBlock "fcn"
DstPort 1
}
Branch {
Points [20, 0; 0, 40]
DstBlock "fcn1"
DstPort 1
}
}
Line {
SrcBlock "-idr"
SrcPort 1
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "delta"
SrcPort 1
DstBlock "Mux"
DstPort 3
}
}
}
Block {
BlockType Outport
Name "out_|Vt|"
Position [580, 30, 600, 50]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_|It|"
Position [640, 55, 660, 75]
Port "2"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_Pgen"
Position [580, 80, 600, 100]
Port "3"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_Qgen"
Position [640, 105, 660, 125]
Port "4"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_delta_gen"
Position [630, 180, 650, 200]
Port "5"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_Tem"
Position [625, 230, 645, 250]
Port "6"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_(wr-we)/wb"
Position [695, 255, 715, 275]
Port "7"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_iqe"
Position [525, 375, 545, 395]
Port "8"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_ide"
Position [625, 400, 645, 420]
Port "9"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_LPA-LPB"
Position [625, 280, 645, 300]
Port "10"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_Gen-Exc"
Position [695, 305, 715, 325]
Port "11"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "Rotor"
SrcPort 2
Points [0, 0]
Branch {
Points [15, 0; 0, -75]
DstBlock "prod1"
DstPort 2
}
Branch {
Points [15, 0; 0, -45]
DstBlock "prod2"
DstPort 2
}
}
Line {
SrcBlock "d_cct"
SrcPort 1
Points [0, 0]
Branch {
Points [50, 0; 0, -180]
DstBlock "prod1"
DstPort 1
}
Branch {
Points [125, 0; 0, -75]
DstBlock "Rotor"
DstPort 2
}
}
Line {
SrcBlock "prod2"
SrcPort 1
Points [-70, 0; 0, 170]
DstBlock "d_cct"
DstPort 2
}
Line {
SrcBlock "Rotor"
SrcPort 3
DstBlock "out_Tem"
DstPort 1
}
Line {
SrcBlock "in_Ef"
SrcPort 1
DstBlock "d_cct"
DstPort 3
}
Line {
SrcBlock "Rotor"
SrcPort 4
DstBlock "out_(wr-we)/wb"
DstPort 1
}
Line {
SrcBlock "in_Tmech"
SrcPort 1
DstBlock "Rotor"
DstPort 5
}
Line {
SrcBlock "d_cct"
SrcPort 2
Points [0, 0]
Branch {
Points [75, 0; 0, -45]
DstBlock "Rotor"
DstPort 4
}
Branch {
Points [75, 0; 0, -210]
DstBlock "PQgen"
DstPort 4
}
Branch {
Points [75, 0; 0, 70]
DstBlock "qdr2qde"
DstPort 2
}
}
Line {
SrcBlock "qde2qdr"
SrcPort 2
Points [0, 0]
Branch {
Points [40, 0; 0, 25]
DstBlock "d_cct"
DstPort 1
}
Branch {
Points [40, 0; 0, -195]
DstBlock "PQgen"
DstPort 3
}
}
Line {
SrcBlock "in_vqse"
SrcPort 1
DstBlock "qde2qdr"
DstPort 1
}
Line {
SrcBlock "in_vdse"
SrcPort 1
DstBlock "qde2qdr"
DstPort 2
}
Line {
SrcBlock "Rotor"
SrcPort 1
Points [0, 0]
Branch {
DstBlock "out_delta_gen"
DstPort 1
}
Branch {
Points [45, 0; 0, 255; -185, 0; 0, -35]
DstBlock "qdr2qde"
DstPort 3
}
Branch {
Points [45, 0; 0, 255; -475, 0; 0, -155]
DstBlock "qde2qdr"
DstPort 3
}
}
Line {
SrcBlock "q_cct"
SrcPort 2
Points [0, 0]
Branch {
Points [100, 0; 0, -165]
DstBlock "PQgen"
DstPort 2
}
Branch {
Points [100, 0; 0, 150]
DstBlock "qdr2qde"
DstPort 1
}
Branch {
Points [100, 0; 0, 25]
DstBlock "Rotor"
DstPort 3
}
}
Line {
SrcBlock "q_cct"
SrcPort 1
Points [0, 0]
Branch {
Points [60, 0; 0, -50]
DstBlock "prod2"
DstPort 1
}
Branch {
DstBlock "Rotor"
DstPort 1
}
}
Line {
SrcBlock "qdr2qde"
SrcPort 1
DstBlock "out_iqe"
DstPort 1
}
Line {
SrcBlock "qdr2qde"
SrcPort 2
DstBlock "out_ide"
DstPort 1
}
Line {
SrcBlock "PQgen"
SrcPort 1
DstBlock "out_|Vt|"
DstPort 1
}
Line {
SrcBlock "PQgen"
SrcPort 3
DstBlock "out_Pgen"
DstPort 1
}
Line {
SrcBlock "PQgen"
SrcPort 4
DstBlock "out_Qgen"
DstPort 1
}
Line {
SrcBlock "PQgen"
SrcPort 2
DstBlock "out_|It|"
DstPort 1
}
Line {
SrcBlock "qde2qdr"
SrcPort 1
Points [0, 0]
Branch {
Points [25, 0; 0, -210]
DstBlock "PQgen"
DstPort 1
}
Branch {
Points [25, 0; 0, -35]
DstBlock "q_cct"
DstPort 1
}
}
Line {
SrcBlock "prod1"
SrcPort 1
Points [-25, 0; 0, 115]
DstBlock "q_cct"
DstPort 2
}
Line {
SrcBlock "Rotor"
SrcPort 5
DstBlock "out_LPA-LPB"
DstPort 1
}
Line {
SrcBlock "Rotor"
SrcPort 6
DstBlock "out_Gen-Exc"
DstPort 1
}
Line {
SrcBlock "q_cct"
SrcPort 3
DstBlock "T"
DstPort 1
}
Line {
SrcBlock "d_cct"
SrcPort 3
DstBlock "T1"
DstPort 1
}
Line {
SrcBlock "d_cct"
SrcPort 4
DstBlock "T2"
DstPort 1
}
Annotation {
Position [192, 272]
VerticalAlignment top
Text "vdr"
}
Annotation {
Position [190, 230]
VerticalAlignment top
Text "vqr"
}
Annotation {
Position [587, 162]
VerticalAlignment top
Text "wr/wb"
}
Annotation {
Position [327, 289]
VerticalAlignment top
Text "psid"
}
Annotation {
Position [327, 194]
VerticalAlignment top
Text "psiq"
}
Annotation {
Position [322, 214]
VerticalAlignment top
Text "-iqr"
}
Annotation {
Position [322, 314]
VerticalAlignment top
Text "-idr"
}
}
}
Block {
BlockType Outport
Name "Out_|Vt|"
Position [320, 30, 340, 50]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "Out_Pgen"
Position [255, 60, 275, 80]
Port "2"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "Out_Qgen"
Position [330, 75, 350, 95]
Port "3"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "Out_slip"
Position [260, 120, 280, 140]
Port "4"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "In_Ef"
SrcPort 1
DstBlock "gen"
DstPort 3
}
Line {
SrcBlock "In_Tmech"
SrcPort 1
DstBlock "gen"
DstPort 4
}
Line {
SrcBlock "gen"
SrcPort 3
DstBlock "Out_Pgen"
DstPort 1
}
Line {
SrcBlock "gen"
SrcPort 4
DstBlock "Out_Qgen"
DstPort 1
}
Line {
SrcBlock "gen"
SrcPort 1
DstBlock "Out_|Vt|"
DstPort 1
}
Line {
SrcBlock "gen"
SrcPort 7
DstBlock "Out_slip"
DstPort 1
}
Line {
SrcBlock "In_Vq4"
SrcPort 1
DstBlock "gen"
DstPort 1
}
Line {
SrcBlock "In_Vd4"
SrcPort 1
DstBlock "gen"
DstPort 2
}
Line {
SrcBlock "gen"
SrcPort 2
DstBlock "T"
DstPort 1
}
Line {
SrcBlock "gen"
SrcPort 5
DstBlock "T1"
DstPort 1
}
Line {
SrcBlock "gen"
SrcPort 6
DstBlock "T2"
DstPort 1
}
Line {
SrcBlock "gen"
SrcPort 8
DstBlock "T3"
DstPort 1
}
Line {
SrcBlock "gen"
SrcPort 9
DstBlock "T4"
DstPort 1
}
Line {
SrcBlock "gen"
SrcPort 10
DstBlock "T5"
DstPort 1
}
Line {
SrcBlock "gen"
SrcPort 11
DstBlock "T6"
DstPort 1
}
}
}
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