📄 s5a.mdl
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Model {
Name "s5a"
Version 2.00
SimParamPage Solver
SampleTimeColors off
WideVectorLines off
PaperOrientation landscape
StartTime "0.0"
StopTime "tstop"
Solver ode113
RelTol "1e-6"
AbsTol "1e-5"
Refine "1"
MaxStep "1e-2"
InitialStep "auto"
FixedStep "auto"
MaxOrder 5
OutputOption RefineOutputTimes
OutputTimes "[]"
LoadExternalInput off
ExternalInput "[t, u]"
SaveTime off
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput off
OutputSaveName "yout"
LoadInitialState off
InitialState "xInitial"
SaveFinalState off
FinalStateName "xFinal"
LimitMaxRows off
MaxRows "1000"
Decimation "1"
AlgebraicLoopMsg warning
MinStepSizeMsg warning
UnconnectedInputMsg warning
UnconnectedOutputMsg warning
UnconnectedLineMsg warning
ConsistencyChecking off
ZeroCross on
BlockDefaults {
Orientation right
ForegroundColor black
BackgroundColor white
DropShadow off
NamePlacement normal
FontName "Helvetica"
FontSize 10
FontWeight normal
FontAngle normal
ShowName on
}
AnnotationDefaults {
HorizontalAlignment center
VerticalAlignment middle
ForegroundColor black
BackgroundColor white
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight normal
FontAngle normal
}
System {
Name "s5a"
Location [20, 62, 752, 544]
Open on
ScreenColor white
Block {
BlockType Clock
Name "Clock"
Position [141, 65, 169, 90]
Orientation up
DeleteFcn "simclock BlockIsBeingDestroyed"
PostSaveFcn "simclock Save"
Location [30, 40, 140, 75]
}
Block {
BlockType SubSystem
Name "Daxis"
Position [390, 295, 425, 350]
ShowPortLabels off
System {
Name "Daxis"
Location [213, 440, 1045, 854]
Open off
ScreenColor white
Block {
BlockType Inport
Name "in_vds"
Position [50, 140, 70, 160]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "in_(wr/wb)*psiqr'"
Position [45, 290, 65, 310]
Port "2"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Fcn
Name "Fcn"
Position [145, 135, 310, 165]
Expr "wb*(u[2]+(rs/xls)*(u[1]-u[3]))"
}
Block {
BlockType Fcn
Name "Fcn2"
Position [145, 284, 325, 316]
Expr "wb*(-u[2] +(rpr/xplr)*(u[3]-u[1]))"
}
Block {
BlockType Fcn
Name "Fcn3"
Position [485, 207, 635, 243]
Expr "xM*(u[1]/xls+u[2]/xplr)"
}
Block {
BlockType Fcn
Name "Fcn4"
Position [495, 126, 585, 154]
Expr "(u[1]-u[2])/xls"
}
Block {
BlockType Fcn
Name "Fcn5"
Position [490, 300, 585, 330]
Expr "(u[1]-u[2])/xplr"
}
Block {
BlockType Mux
Name "Mux"
Position [100, 108, 120, 192]
Inputs "3"
}
Block {
BlockType Mux
Name "Mux1"
Position [105, 262, 125, 338]
Inputs "3"
}
Block {
BlockType Mux
Name "Mux2"
Position [450, 286, 470, 339]
Inputs "2"
}
Block {
BlockType Mux
Name "Mux3"
Position [445, 193, 465, 257]
Inputs "2"
}
Block {
BlockType Mux
Name "Mux4"
Position [450, 114, 470, 161]
Inputs "2"
}
Block {
BlockType Integrator
Name "psidr'_"
Position [345, 287, 375, 313]
ExternalReset none
InitialConditionSource internal
InitialCondition "Psipdro"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
}
Block {
BlockType Integrator
Name "psids_"
Position [335, 137, 365, 163]
ExternalReset none
InitialConditionSource internal
InitialCondition "Psidso"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
}
Block {
BlockType Outport
Name "out_psids"
Position [735, 65, 755, 85]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_ids"
Position [735, 130, 755, 150]
Port "2"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_idr'"
Position [735, 305, 755, 325]
Port "3"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_psidr'"
Position [735, 260, 755, 280]
Port "4"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "Fcn5"
SrcPort 1
DstBlock "out_idr'"
DstPort 1
}
Line {
SrcBlock "in_(wr/wb)*psiqr'"
SrcPort 1
DstBlock "Mux1"
DstPort 2
}
Line {
SrcBlock "in_vds"
SrcPort 1
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "Fcn4"
SrcPort 1
DstBlock "out_ids"
DstPort 1
}
Line {
SrcBlock "Mux"
SrcPort 1
DstBlock "Fcn"
DstPort 1
}
Line {
SrcBlock "Fcn"
SrcPort 1
DstBlock "psids_"
DstPort 1
}
Line {
SrcBlock "Fcn2"
SrcPort 1
DstBlock "psidr'_"
DstPort 1
}
Line {
SrcBlock "Mux3"
SrcPort 1
DstBlock "Fcn3"
DstPort 1
}
Line {
SrcBlock "Mux4"
SrcPort 1
DstBlock "Fcn4"
DstPort 1
}
Line {
SrcBlock "psids_"
SrcPort 1
Points [0, 0]
Branch {
Points [35, 0; 0, -75]
DstBlock "out_psids"
DstPort 1
}
Branch {
Points [35, 0; 0, 60]
DstBlock "Mux3"
DstPort 1
}
Branch {
Points [35, 0; 0, -25]
DstBlock "Mux4"
DstPort 1
}
Branch {
Points [35, 0; 0, 60; -325, 0; 0, -30]
DstBlock "Mux"
DstPort 3
}
}
Line {
SrcBlock "Fcn3"
SrcPort 1
Points [0, 0]
Branch {
Points [55, 0; 0, -45; -270, 0; 0, -30]
DstBlock "Mux4"
DstPort 2
}
Branch {
Points [55, 0; 0, 140; -620, 0; 0, -40]
DstBlock "Mux1"
DstPort 3
}
Branch {
Points [55, 0; 0, -135; -615, 0; 0, 30]
DstBlock "Mux"
DstPort 1
}
Branch {
Points [55, 0; 0, 140; -285, 0; 0, -40]
DstBlock "Mux2"
DstPort 2
}
}
Line {
SrcBlock "Mux1"
SrcPort 1
DstBlock "Fcn2"
DstPort 1
}
Line {
SrcBlock "psidr'_"
SrcPort 1
Points [0, 0]
Branch {
Points [35, 0; 0, -30]
DstBlock "out_psidr'"
DstPort 1
}
Branch {
Points [35, 0; 0, -60; -330, 0; 0, 35]
DstBlock "Mux1"
DstPort 1
}
Branch {
Points [35, 0; 0, -60]
DstBlock "Mux3"
DstPort 2
}
Branch {
DstBlock "Mux2"
DstPort 1
}
}
Line {
SrcBlock "Mux2"
SrcPort 1
DstBlock "Fcn5"
DstPort 1
}
Annotation {
Position [392, 283]
VerticalAlignment top
Text "psidr'"
}
Annotation {
Position [602, 299]
VerticalAlignment top
Text "idr'"
}
Annotation {
Position [667, 207]
VerticalAlignment top
Text "psiqm"
}
Annotation {
Position [382, 132]
VerticalAlignment top
Text "psids"
}
Annotation {
Position [602, 127]
VerticalAlignment top
Text "ids"
}
}
}
Block {
BlockType Fcn
Name "Fcn"
Position [80, 166, 210, 194]
Expr "Vm*cos(u[1])"
}
Block {
BlockType Fcn
Name "Fcn1"
Position [80, 215, 210, 245]
Expr "Vm*cos(u[1]-2*pi/3)"
}
Block {
BlockType Fcn
Name "Fcn2"
Position [80, 266, 210, 294]
Expr "Vm*cos(u[1]+2*pi/3)"
}
Block {
BlockType SubSystem
Name "m5"
Position [106, 322, 176, 359]
DropShadow on
OpenFcn "m5"
ShowPortLabels off
MaskType "Masked block of m5.m"
MaskHelp "Uses m5.m to initialize and plot"
MaskDisplay "disp('Initialize\\nand plot')"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate off
MaskIconUnits autoscale
System {
Name "m5"
Location [25, 32767, 317, 32767]
Open off
ScreenColor white
Annotation {
Position [142, 50]
VerticalAlignment top
Text "Uses m5.m to initIalize simulation \nand "
"plot results"
}
}
}
Block {
BlockType Mux
Name "Mux"
Position [520, 46, 545, 114]
Inputs "6"
}
Block {
BlockType Product
Name "Product"
Position [420, 189, 440, 211]
Orientation left
Inputs "2"
}
Block {
BlockType Product
Name "Product1"
Position [420, 238, 440, 262]
Orientation left
Inputs "2"
}
Block {
BlockType SubSystem
Name "Qaxis"
Position [385, 120, 420, 175]
ShowPortLabels off
System {
Name "Qaxis"
Location [213, 440, 1045, 854]
Open off
ScreenColor white
Block {
BlockType Inport
Name "in_vqs"
Position [50, 140, 70, 160]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "in_(wr/wb)*psidr'"
Position [45, 290, 65, 310]
Port "2"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Fcn
Name "Fcn"
Position [145, 135, 310, 165]
Expr "wb*(u[2]+(rs/xls)*(u[1]-u[3]))"
}
Block {
BlockType Fcn
Name "Fcn2"
Position [145, 284, 325, 316]
Expr "wb*(u[2] +(rpr/xplr)*(u[3]-u[1]))"
}
Block {
BlockType Fcn
Name "Fcn3"
Position [485, 207, 635, 243]
Expr "xM*(u[1]/xls+u[2]/xplr)"
}
Block {
BlockType Fcn
Name "Fcn4"
Position [495, 126, 585, 154]
Expr "(u[1]-u[2])/xls"
}
Block {
BlockType Fcn
Name "Fcn5"
Position [490, 300, 585, 330]
Expr "(u[1]-u[2])/xplr"
}
Block {
BlockType Mux
Name "Mux"
Position [100, 108, 120, 192]
Inputs "3"
}
Block {
BlockType Mux
Name "Mux1"
Position [105, 262, 125, 338]
Inputs "3"
}
Block {
BlockType Mux
Name "Mux2"
Position [450, 286, 470, 339]
Inputs "2"
}
Block {
BlockType Mux
Name "Mux3"
Position [445, 193, 465, 257]
Inputs "2"
}
Block {
BlockType Mux
Name "Mux4"
Position [450, 114, 470, 161]
Inputs "2"
}
Block {
BlockType Integrator
Name "psiqr'_"
Position [345, 287, 375, 313]
ExternalReset none
InitialConditionSource internal
InitialCondition "Psipqro"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
}
Block {
BlockType Integrator
Name "psiqs_"
Position [335, 137, 365, 163]
ExternalReset none
InitialConditionSource internal
InitialCondition "Psiqso"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
}
Block {
BlockType Outport
Name "out_psiqs"
Position [735, 65, 755, 85]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_iqs"
Position [735, 130, 755, 150]
Port "2"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_iqr'"
Position [735, 305, 755, 325]
Port "3"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_psiqr'"
Position [735, 260, 755, 280]
Port "4"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "Fcn5"
SrcPort 1
DstBlock "out_iqr'"
DstPort 1
}
Line {
SrcBlock "in_(wr/wb)*psidr'"
SrcPort 1
DstBlock "Mux1"
DstPort 2
}
Line {
SrcBlock "in_vqs"
SrcPort 1
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "Fcn4"
SrcPort 1
DstBlock "out_iqs"
DstPort 1
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