📄 s6.mdl
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Position [205, 248, 235, 272]
Operator <
}
Block {
BlockType SubSystem
Name "S-R\nFlip-Flop"
Position [355, 313, 380, 357]
ShowPortLabels on
System {
Name "S-R\nFlip-Flop"
Location [519, 396, 821, 598]
Open off
ScreenColor white
Block {
BlockType Inport
Name "S"
Position [25, 105, 45, 125]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "R"
Position [25, 145, 45, 165]
Port "2"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Demux
Name "Demux"
Position [175, 66, 180, 159]
Outputs "2"
}
Block {
BlockType CombinatorialLogic
Name "Logic"
Position [115, 99, 145, 131]
TruthTable "[0 1;0 1;1 0;0 1;1 0;0 1;1 0;1 0]"
}
Block {
BlockType Memory
Name "Memory"
Position [115, 25, 155, 55]
Orientation left
X0 "0"
InheritSampleTime on
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate off
MaskIconUnits autoscale
}
Block {
BlockType Mux
Name "Mux"
Position [90, 54, 95, 176]
Inputs "3"
}
Block {
BlockType Outport
Name "Q"
Position [255, 80, 275, 100]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "!Q"
Position [255, 125, 275, 145]
Port "2"
OutputWhenDisabled held
InitialOutput "1"
}
Line {
SrcBlock "R"
SrcPort 1
DstBlock "Mux"
DstPort 3
}
Line {
SrcBlock "S"
SrcPort 1
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "Memory"
SrcPort 1
Points [-50, 0; 0, 35]
DstBlock "Mux"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 1
Points [25, 0]
Branch {
Points [0, -50]
DstBlock "Memory"
DstPort 1
}
Branch {
DstBlock "Q"
DstPort 1
}
}
Line {
SrcBlock "Demux"
SrcPort 2
DstBlock "!Q"
DstPort 1
}
Line {
SrcBlock "Logic"
SrcPort 1
DstBlock "Demux"
DstPort 1
}
Line {
SrcBlock "Mux"
SrcPort 1
DstBlock "Logic"
DstPort 1
}
}
}
Block {
BlockType SubSystem
Name "S-R\nFlip-Flop1"
Position [230, 323, 255, 367]
ShowPortLabels on
System {
Name "S-R\nFlip-Flop1"
Location [519, 396, 821, 598]
Open off
ScreenColor white
Block {
BlockType Inport
Name "S"
Position [25, 105, 45, 125]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "R"
Position [25, 145, 45, 165]
Port "2"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Demux
Name "Demux"
Position [175, 66, 180, 159]
Outputs "2"
}
Block {
BlockType CombinatorialLogic
Name "Logic"
Position [115, 99, 145, 131]
TruthTable "[0 1;0 1;1 0;0 1;1 0;0 1;1 0;1 0]"
}
Block {
BlockType Memory
Name "Memory"
Position [115, 25, 155, 55]
Orientation left
X0 "0"
InheritSampleTime on
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate off
MaskIconUnits autoscale
}
Block {
BlockType Mux
Name "Mux"
Position [90, 54, 95, 176]
Inputs "3"
}
Block {
BlockType Outport
Name "Q"
Position [255, 80, 275, 100]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "!Q"
Position [255, 125, 275, 145]
Port "2"
OutputWhenDisabled held
InitialOutput "1"
}
Line {
SrcBlock "R"
SrcPort 1
DstBlock "Mux"
DstPort 3
}
Line {
SrcBlock "S"
SrcPort 1
DstBlock "Mux"
DstPort 2
}
Line {
SrcBlock "Memory"
SrcPort 1
Points [-50, 0; 0, 35]
DstBlock "Mux"
DstPort 1
}
Line {
SrcBlock "Demux"
SrcPort 1
Points [25, 0]
Branch {
Points [0, -50]
DstBlock "Memory"
DstPort 1
}
Branch {
DstBlock "Q"
DstPort 1
}
}
Line {
SrcBlock "Demux"
SrcPort 2
DstBlock "!Q"
DstPort 1
}
Line {
SrcBlock "Logic"
SrcPort 1
DstBlock "Demux"
DstPort 1
}
Line {
SrcBlock "Mux"
SrcPort 1
DstBlock "Logic"
DstPort 1
}
}
}
Block {
BlockType Sum
Name "Sum"
Position [410, 90, 430, 125]
Inputs "++"
}
Block {
BlockType Sum
Name "Sum2"
Position [580, 101, 600, 139]
Inputs "+-"
}
Block {
BlockType Switch
Name "Switch"
Position [530, 103, 550, 157]
Threshold "0.5"
}
Block {
BlockType Switch
Name "Switch1"
Position [325, 51, 340, 109]
Threshold "0.5"
}
Block {
BlockType Switch
Name "Switch2"
Position [320, 141, 335, 199]
Threshold "0.5"
}
Block {
BlockType Switch
Name "Switch3"
Position [640, 73, 660, 127]
Threshold "0.5"
}
Block {
BlockType Switch
Name "Switch4"
Position [100, 143, 120, 197]
Threshold "0.5"
}
Block {
BlockType Terminator
Name "T"
Position [275, 350, 285, 360]
}
Block {
BlockType Terminator
Name "T1"
Position [405, 340, 415, 350]
}
Block {
BlockType Integrator
Name "Vcap_"
Position [355, 155, 385, 185]
ExternalReset none
InitialConditionSource internal
InitialCondition "0"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
}
Block {
BlockType Fcn
Name "abs(i'ds)"
Position [120, 240, 160, 270]
Expr "abs(u[1])"
}
Block {
BlockType Constant
Name "cutoff\nspeed"
Position [65, 357, 130, 383]
Value "wrswbywb"
}
Block {
BlockType Constant
Name "eps"
Position [120, 295, 155, 315]
Value "5e-2"
}
Block {
BlockType Outport
Name "out_vqs"
Position [685, 15, 705, 35]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_v'ds"
Position [700, 90, 720, 110]
Port "2"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "out_Vcap"
Position [690, 165, 710, 185]
Port "3"
OutputWhenDisabled held
InitialOutput "0"
}
Line {
SrcBlock "Sum"
SrcPort 1
Points [35, 0]
Branch {
DstBlock "Switch"
DstPort 1
}
Branch {
Points [-30, 0; 0, 65]
DstBlock "out_Vcap"
DstPort 1
}
}
Line {
SrcBlock "Switch"
SrcPort 1
DstBlock "Sum2"
DstPort 2
}
Line {
SrcBlock "Logical\nOperator2"
SrcPort 1
Points [0, 0]
Branch {
Points [0, -10; -45, 0; 0, 30; -405, 0; 0, -50]
DstBlock "Switch4"
DstPort 2
}
Branch {
Points [0, -70]
DstBlock "Switch"
DstPort 2
}
}
Line {
SrcBlock "in_i'ds"
SrcPort 1
Points [-15, 0]
Branch {
DstBlock "Switch4"
DstPort 1
}
Branch {
Points [20, 0; 0, 105]
DstBlock "abs(i'ds)"
DstPort 1
}
}
Line {
SrcBlock "S-R\nFlip-Flop"
SrcPort 1
Points [5, 0]
Branch {
DstBlock "Logical\nOperator3"
DstPort 2
}
Branch {
Points [5, 0; 0, -55]
DstBlock "Logical\nOperator1"
DstPort 2
}
}
Line {
SrcBlock "Capstart"
SrcPort 1
Points [0, 0]
Branch {
Points [-20, 0; 0, 50]
DstBlock "Logical\nOperator3"
DstPort 1
}
Branch {
Points [-20, 0]
DstBlock "Logical\nOperator2"
DstPort 2
}
}
Line {
SrcBlock "Caprun"
SrcPort 1
Points [0, 0]
Branch {
Points [-10, 0; 0, -15]
DstBlock "Logical\nOperator2"
DstPort 1
}
Branch {
DstBlock "Logical\nOperator1"
DstPort 1
}
}
Line {
SrcBlock "1/Crun"
SrcPort 1
DstBlock "Switch2"
DstPort 1
}
Line {
SrcBlock "1/Cstart"
SrcPort 1
DstBlock "Switch2"
DstPort 3
}
Line {
SrcBlock "Rcrun"
SrcPort 1
DstBlock "Switch1"
DstPort 1
}
Line {
SrcBlock "Rcstart"
SrcPort 1
DstBlock "Switch1"
DstPort 3
}
Line {
SrcBlock "Logical\nOperator1"
SrcPort 1
Points [0, 0]
Branch {
Points [-10, 0; 0, -185]
DstBlock "Switch1"
DstPort 2
}
Branch {
Points [-10, 0; 0, -95]
DstBlock "Switch2"
DstPort 2
}
}
Line {
SrcBlock "Switch1"
SrcPort 1
Points [45, 0; 0, 20]
DstBlock "Sum"
DstPort 1
}
Line {
SrcBlock "Logical\nOperator"
SrcPort 1
DstBlock "S-R\nFlip-Flop"
DstPort 1
}
Line {
SrcBlock "Rel Op1"
SrcPort 1
Points [20, 0; 0, 55]
DstBlock "Logical\nOperator"
DstPort 1
}
Line {
SrcBlock "eps"
SrcPort 1
Points [10, 0; 0, -40]
DstBlock "Rel Op1"
DstPort 2
}
Line {
SrcBlock "abs(i'ds)"
SrcPort 1
DstBlock "Rel Op1"
DstPort 1
}
Line {
SrcBlock "cutoff\nspeed"
SrcPort 1
Points [15, 0; 0, -30]
DstBlock "Rel Op"
DstPort 2
}
Line {
SrcBlock "in_wr/wb"
SrcPort 1
DstBlock "Rel Op"
DstPort 1
}
Line {
SrcBlock "Gain2"
SrcPort 1
Points [0, 45]
DstBlock "Sum2"
DstPort 1
}
Line {
SrcBlock "in_vas"
SrcPort 1
Points [0, 0]
Branch {
Points [375, 0; 0, 40]
DstBlock "Gain2"
DstPort 1
}
Branch {
DstBlock "out_vqs"
DstPort 1
}
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