📄 s2.mdl
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Model {
Name "s2"
Version 2.00
SimParamPage Solver
SampleTimeColors off
WideVectorLines off
PaperOrientation landscape
StartTime "0.0"
StopTime "5"
Solver ode15s
RelTol "1e-6"
AbsTol "1e-6"
Refine "1"
MaxStep "0.005"
InitialStep "auto"
FixedStep "auto"
MaxOrder 5
OutputOption RefineOutputTimes
OutputTimes "[]"
LoadExternalInput off
ExternalInput "[t, u]"
SaveTime off
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput off
OutputSaveName "yout"
LoadInitialState off
InitialState "xInitial"
SaveFinalState off
FinalStateName "xFinal"
LimitMaxRows off
MaxRows "1000"
Decimation "1"
AlgebraicLoopMsg warning
MinStepSizeMsg warning
UnconnectedInputMsg warning
UnconnectedOutputMsg warning
UnconnectedLineMsg warning
ConsistencyChecking off
ZeroCross on
BlockDefaults {
Orientation right
ForegroundColor black
BackgroundColor white
DropShadow off
NamePlacement normal
FontName "Helvetica"
FontSize 10
FontWeight normal
FontAngle normal
ShowName on
}
AnnotationDefaults {
HorizontalAlignment center
VerticalAlignment middle
ForegroundColor black
BackgroundColor white
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight normal
FontAngle normal
}
System {
Name "s2"
Location [63, 66, 783, 583]
Open on
ScreenColor white
Block {
BlockType Gain
Name "1/J"
Position [495, 164, 540, 206]
Gain "1/J"
}
Block {
BlockType Gain
Name "1/Laq"
Position [180, 189, 225, 231]
Gain "1/Laq"
}
Block {
BlockType Switch
Name "C1"
Position [115, 299, 130, 341]
Orientation left
Threshold "0.5"
}
Block {
BlockType Switch
Name "C2"
Position [135, 354, 150, 396]
Orientation left
Threshold "0.5"
}
Block {
BlockType Switch
Name "C3"
Position [155, 408, 170, 452]
Orientation left
Threshold "0.5"
}
Block {
BlockType Clock
Name "Clock"
Position [250, 83, 265, 97]
NamePlacement alternate
DeleteFcn "simclock BlockIsBeingDestroyed"
PostSaveFcn "simclock Save"
Location [30, 40, 140, 75]
}
Block {
BlockType Gain
Name "D"
Position [505, 125, 560, 155]
Orientation left
Gain "D"
}
Block {
BlockType SubSystem
Name "D Latch"
Position [380, 260, 405, 295]
ShowPortLabels on
System {
Name "D Latch"
Location [470, 422, 684, 597]
Open off
ScreenColor white
Block {
BlockType Inport
Name "D"
Position [25, 83, 55, 97]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "C"
Position [80, 15, 110, 30]
Orientation down
Port "2"
PortWidth "-1"
SampleTime "-1"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate off
MaskIconUnits autoscale
}
Block {
BlockType SubSystem
Name "D Latch"
Position [75, 51, 115, 124]
ShowPortLabels on
System {
Name "D Latch"
Location [756, 470, 1027, 609]
Open off
ScreenColor white
Block {
BlockType Inport
Name "D"
Position [25, 55, 45, 75]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType EnablePort
Name "C"
Position [15, 15, 35, 35]
StatesWhenEnabling held
ShowOutputPort off
}
Block {
BlockType Logic
Name "Logic"
Position [135, 93, 165, 117]
Operator NOT
Inputs "1"
}
Block {
BlockType Outport
Name "Q"
Position [205, 55, 225, 75]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "!Q"
Position [205, 95, 225, 115]
Port "2"
OutputWhenDisabled held
InitialOutput "1"
}
Line {
SrcBlock "D"
SrcPort 1
Points [50, 0]
Branch {
Points [0, 40]
DstBlock "Logic"
DstPort 1
}
Branch {
DstBlock "Q"
DstPort 1
}
}
Line {
SrcBlock "Logic"
SrcPort 1
DstBlock "!Q"
DstPort 1
}
}
}
Block {
BlockType Outport
Name "Q"
Position [140, 63, 170, 77]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "!Q"
Position [140, 98, 170, 112]
Port "2"
OutputWhenDisabled held
InitialOutput "1"
}
Line {
SrcBlock "D Latch"
SrcPort 2
DstBlock "!Q"
DstPort 1
}
Line {
SrcBlock "D"
SrcPort 1
DstBlock "D Latch"
DstPort 1
}
Line {
SrcBlock "D Latch"
SrcPort 1
DstBlock "Q"
DstPort 1
}
Line {
SrcBlock "C"
SrcPort 1
DstBlock "D Latch"
DstPort enable
}
}
}
Block {
BlockType SubSystem
Name "D Latch1"
Position [500, 260, 525, 295]
ShowPortLabels on
System {
Name "D Latch1"
Location [516, 424, 730, 599]
Open off
ScreenColor white
Block {
BlockType Inport
Name "D"
Position [25, 83, 55, 97]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "C"
Position [80, 15, 110, 30]
Orientation down
Port "2"
PortWidth "-1"
SampleTime "-1"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate off
MaskIconUnits autoscale
}
Block {
BlockType SubSystem
Name "D Latch"
Position [75, 51, 115, 124]
ShowPortLabels on
System {
Name "D Latch"
Location [756, 470, 1027, 609]
Open off
ScreenColor white
Block {
BlockType Inport
Name "D"
Position [25, 55, 45, 75]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType EnablePort
Name "C"
Position [15, 15, 35, 35]
StatesWhenEnabling held
ShowOutputPort off
}
Block {
BlockType Logic
Name "Logic"
Position [135, 93, 165, 117]
Operator NOT
Inputs "1"
}
Block {
BlockType Outport
Name "Q"
Position [205, 55, 225, 75]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "!Q"
Position [205, 95, 225, 115]
Port "2"
OutputWhenDisabled held
InitialOutput "1"
}
Line {
SrcBlock "D"
SrcPort 1
Points [50, 0]
Branch {
Points [0, 40]
DstBlock "Logic"
DstPort 1
}
Branch {
DstBlock "Q"
DstPort 1
}
}
Line {
SrcBlock "Logic"
SrcPort 1
DstBlock "!Q"
DstPort 1
}
}
}
Block {
BlockType Outport
Name "Q"
Position [140, 63, 170, 77]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "!Q"
Position [140, 98, 170, 112]
Port "2"
OutputWhenDisabled held
InitialOutput "1"
}
Line {
SrcBlock "D Latch"
SrcPort 2
DstBlock "!Q"
DstPort 1
}
Line {
SrcBlock "D"
SrcPort 1
DstBlock "D Latch"
DstPort 1
}
Line {
SrcBlock "D Latch"
SrcPort 1
DstBlock "Q"
DstPort 1
}
Line {
SrcBlock "C"
SrcPort 1
DstBlock "D Latch"
DstPort enable
}
}
}
Block {
BlockType SubSystem
Name "D Latch2"
Position [620, 261, 645, 294]
ShowPortLabels on
System {
Name "D Latch2"
Location [516, 424, 730, 599]
Open off
ScreenColor white
Block {
BlockType Inport
Name "D"
Position [25, 83, 55, 97]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType Inport
Name "C"
Position [80, 15, 110, 30]
Orientation down
Port "2"
PortWidth "-1"
SampleTime "-1"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate off
MaskIconUnits autoscale
}
Block {
BlockType SubSystem
Name "D Latch"
Position [75, 51, 115, 124]
ShowPortLabels on
System {
Name "D Latch"
Location [756, 470, 1027, 609]
Open off
ScreenColor white
Block {
BlockType Inport
Name "D"
Position [25, 55, 45, 75]
Port "1"
PortWidth "-1"
SampleTime "-1"
}
Block {
BlockType EnablePort
Name "C"
Position [15, 15, 35, 35]
StatesWhenEnabling held
ShowOutputPort off
}
Block {
BlockType Logic
Name "Logic"
Position [135, 93, 165, 117]
Operator NOT
Inputs "1"
}
Block {
BlockType Outport
Name "Q"
Position [205, 55, 225, 75]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "!Q"
Position [205, 95, 225, 115]
Port "2"
OutputWhenDisabled held
InitialOutput "1"
}
Line {
SrcBlock "D"
SrcPort 1
Points [50, 0]
Branch {
Points [0, 40]
DstBlock "Logic"
DstPort 1
}
Branch {
DstBlock "Q"
DstPort 1
}
}
Line {
SrcBlock "Logic"
SrcPort 1
DstBlock "!Q"
DstPort 1
}
}
}
Block {
BlockType Outport
Name "Q"
Position [140, 63, 170, 77]
Port "1"
OutputWhenDisabled held
InitialOutput "0"
}
Block {
BlockType Outport
Name "!Q"
Position [140, 98, 170, 112]
Port "2"
OutputWhenDisabled held
InitialOutput "1"
}
Line {
SrcBlock "D Latch"
SrcPort 2
DstBlock "!Q"
DstPort 1
}
Line {
SrcBlock "D"
SrcPort 1
DstBlock "D Latch"
DstPort 1
}
Line {
SrcBlock "D Latch"
SrcPort 1
DstBlock "Q"
DstPort 1
}
Line {
SrcBlock "C"
SrcPort 1
DstBlock "D Latch"
DstPort enable
}
}
}
Block {
BlockType Ground
Name "Ground"
Position [195, 292, 210, 308]
Orientation left
}
Block {
BlockType HitCross
Name "Hit \nCrossing"
Position [325, 260, 345, 280]
HitCrossingOffset "60"
HitCrossingDirection falling
ShowOutputPort on
}
Block {
BlockType Integrator
Name "Integrator"
Position [265, 194, 300, 226]
ExternalReset none
InitialConditionSource internal
InitialCondition "0"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
}
Block {
BlockType Integrator
Name "Integrator2"
Position [565, 169, 595, 201]
ExternalReset none
InitialConditionSource internal
InitialCondition "0"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
}
Block {
BlockType SubSystem
Name "m2"
Position [47, 40, 115, 78]
DropShadow on
OpenFcn "m2"
ShowPortLabels off
MaskType "Masked block of m2.m"
MaskHelp "Uses m2.m to initialize and plot"
MaskDisplay "disp('Initialize\\nand plot')"
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate off
MaskIconUnits autoscale
System {
Name "m2"
Location [110, 32767, 224, 32767]
Open off
ScreenColor white
Annotation {
Position [62, 52]
VerticalAlignment top
Text "Masked block of m2.m in Chapter 8\nto "
"initialize s2.m and plot results"
}
}
}
Block {
BlockType Memory
Name "Memory"
Position [455, 261, 475, 279]
X0 "0"
InheritSampleTime off
}
Block {
BlockType Memory
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