setup.c

读取frv实验系统上的按键值 并以此来控制frv实验板上的led 基于嵌入式linux

/*
 * setup.c
 */

#include <linux/config.h>
#include <linux/init.h>
#include <linux/console.h>
#include <asm/system.h>
#include <asm/page.h>
#include <asm/memory.h>
#include <asm/setup.h>
#include <asm/frvregs.h>
#include <asm/frvirq.h>
#include "fr400pdk2_board.h"

#ifdef CONFIG_SERIAL
#include <linux/serialP.h>
#include <asm/serial.h>
#endif

//#define DEBUG_MB93403_SERIAL

/*******************************************************************/
static int peripheral_clk = 66000000;

#ifdef CONFIG_SERIAL
static inline void write_mb93403_register_u32(u32 reg, u32 val)
{
	*((volatile u32*)reg) = val;
	//__asm__ __volatile__("membar");
}

static inline void write_mb93403_register_u8(u32 reg, u8 val)
{
	*((volatile u8*)reg) = val;
	//__asm__ __volatile__("membar");
}

static inline u8 read_mb93403_register_u8(u32 reg)
{
	//__asm__ __volatile__("membar");
	return *((volatile u8*)reg);
}

static void __init mb93403_uart_init_for_generic_serial_driver(void)
{
/*
66000000/38400/16=107.42
 DL  = 107 = 0x006B
 IER = 0000B = 0x00
 FCR = 00--0000B = 0x00
 LCR = 00000011B = 0x03
 MCR = 0x00
 */
	int gpio=0xfeff0400;
	int uart=0xfeff9c00;
	int dll;

	dll  = peripheral_clk/((38400)*16);
	
/* GPIO */
	//write_mb93403_register_u32(gpio+0x00,0x000fffff); /* PDR */
	//write_mb93403_register_u32(gpio+0x08,0x00000000); /* GPDR */
	write_mb93403_register_u32(gpio+0x10,0x000c954f); /* SIR */
	write_mb93403_register_u32(gpio+0x18,0x00336ab0); /* SOR */
/* UART */
	write_mb93403_register_u8(uart+0x90,0x00); /* UCPSR */
	write_mb93403_register_u8(uart+0x98,0x00); /* UCPVR */
/* UART0 */
	write_mb93403_register_u8(uart+0x18,0x83); /* LCR */
	__asm__ __volatile__("membar");
/*BASIC_SOFT@FUJITSU MOD*/
//	write_mb93403_register_u8(uart+0x00,0x29); /* DLL */
//	write_mb93403_register_u8(uart+0x08,0x00); /* DLM */
	write_mb93403_register_u8(uart+0x00, dll&0x00ff);	/* DLL */
	write_mb93403_register_u8(uart+0x08,(dll>>8)&0x00ff);	/* DLM */
/*BASIC_SOFT@FUJITSU MOD*/
	write_mb93403_register_u8(uart+0x18,0x03); /* LCR */
	__asm__ __volatile__("membar");
	//write_mb93403_register_u8(uart+0x10,0x00); /* FCR */
	write_mb93403_register_u8(uart+0x10,0xc7); /* FCR */
	write_mb93403_register_u8(uart+0x08,0x00); /* IER */
	write_mb93403_register_u8(uart+0x20,0x02); /* MCR */
/* UART1 */
	write_mb93403_register_u8(uart+0x58,0x83); /* LCR */
	__asm__ __volatile__("membar");
/*BASIC_SOFT@FUJITSU MOD*/
//	write_mb93403_register_u8(uart+0x40,0x29); /* DLL */
//	write_mb93403_register_u8(uart+0x48,0x00); /* DLM */
	write_mb93403_register_u8(uart+0x40,dll&0x00ff);	/* DLL */
	write_mb93403_register_u8(uart+0x48,(dll>>8)&0x00ff);	/* DLM */
/*BASIC_SOFT@FUJITSU MOD*/
	write_mb93403_register_u8(uart+0x58,0x03); /* LCR */
	__asm__ __volatile__("membar");
	//write_mb93403_register_u8(uart+0x50,0x00); /* FCR */
	write_mb93403_register_u8(uart+0x50,0xc7); /* FCR */
	write_mb93403_register_u8(uart+0x48,0x00); /* IER */
	//write_mb93403_register_u8(uart+0x60,0x02); /* MCR */
}

void frv_serial_fix_rs_table(struct serial_state *table, int len)
{
    int i, baud_base;

    /*
     * baud_base = peripheral_clk / (UCPVR.VALUE * (1<<UCPSR.SELECT) * 16)
     *            UCPVR.VALUE  = 0x01, UCPVR.SELECT = 0x00
     */

    baud_base = peripheral_clk / 16;

    for( i=0; i < len; i++ ){
	if( table[i].irq == FRV_K_IRQ_UART0 ||
	    table[i].irq == FRV_K_IRQ_UART1 ){
	    table[i].baud_base = baud_base;
	}
    }
}

#endif /* CONFIG_SERIAL */

#ifdef DEBUG_MB93403_SERIAL
#define	UART1BASE	(0xfeff9c00+0x00)
#define	UART2BASE	(0xfeff9c00+0x40)

#define	U_RB	0x00		/* receive buffer */
#define	U_TB	0x00		/* transmit buffer */
#define	U_IER	0x01		/* interrupt enable register */
#define	U_IIR	0x02		/* interrupt identification */
#define	U_FCR	0x02		/* fifo control register */
#define	U_LCR	0x03		/* line control register */
#define	U_MCR	0x04		/* modem control register */
#define	U_LSR	0x05		/* line status register */
#define	U_MSR	0x06		/* modem status register */
#define	U_SCR	0x07		/* scratchpad register */
#define	U_DLL	0x00		/* divisor latch LS-byte */
#define	U_DLM	0x01		/* divisor latch MS-byte */

#define U_UCSLR 0x88
#define U_UCPSR 0x90
#define U_UCPVR 0x98

#define	B9600	12		/* 9600  1.8462Mhz or 1.8432MHz */
#define	B19200	6		/* 19200 1.8462Mhz or 1.8432MHz */
#define	B38400	3		/* 38400 1.8462Mhz or 1.8432MHz */

static void wait_loop(long count);

#define	UART_REG_SET(base, reg, dat) do{ *(unsigned long *)((unsigned char *)base + reg) = (dat<<24) ; wait_loop(1) ; }while(0)
#define	UART_REG_GET(base, reg) (unsigned char)(*(unsigned long *)((unsigned char *)base + reg) >> 24)

static unsigned char *base;
static int scale = 0;

unsigned char UART_GetCharBase()
{
	char status, data ;

	while(1) {
		status = UART_REG_GET(base, U_LSR*scale) ;
		if (status & 0x01) {
			data = UART_REG_GET(base, U_RB*scale) ;
			break ;
		}
		else if (status & 0x0e) {
			data = UART_REG_GET(base, U_RB*scale) ;
			break ;
		}
	}
	return data ;
}

void UART_PutCharBase(char data)
{
	char status ;

	while(1) {
		status = UART_REG_GET(base, U_LSR*scale) ;
		if (status & 0x40) {
			UART_REG_SET(base, U_TB*scale, data) ;
			break ;
		}
	}
}

static void UART_16550_Init(unsigned char *DeviceBase, int port)
{
    UART_REG_SET(DeviceBase, U_UCPSR, 0x80) ;

    /*-- ALL INTERRUPTS DESABLE              */
    UART_REG_SET(DeviceBase, U_IER*scale, 0x00) ;

    /*-- SET DIVISOR LATCH ACCESS BIT        */
    UART_REG_SET(DeviceBase, U_LCR*scale, 0x80) ;

    /*-- SET BAUD RATE VALUE                 */
//  UART_REG_SET(DeviceBase, U_DLL*scale, B9600) ;
    UART_REG_SET(DeviceBase, U_DLL*scale, B38400) ;
    UART_REG_SET(DeviceBase, U_DLM*scale, 0x00) ;

    /*-- 8bit/ 1stop/ no-parity              */
    /*-- SET DIVISOR LATCH ACCESS BIT        */
    UART_REG_SET(DeviceBase, U_LCR*scale, 0x03) ;

    /*-- FIFO ENABLE AND CLEAR               */
    UART_REG_SET(DeviceBase, U_FCR*scale, 0x07) ;

    /*-- DTR, RTS                            */
    UART_REG_SET(DeviceBase, U_MCR*scale, 0x03) ;
}

void mb93403_console_write(struct console *con, const char *buf, unsigned len)
{
    int i;

    for (i = 0; i < len; i++) {
	if (buf[i] == '\n') 
	    UART_PutCharBase('\r');
	UART_PutCharBase(buf[i]);
    }
}

static void __init mb93403_uart_init(void)
{
    int port;

    port = 01;
    base = (unsigned char *)(UART1BASE);
    scale = 8;
    UART_16550_Init(base, port) ;
}

static void wait_loop(long count)
{
  long i;

  for(i=0; i<count; i++);
  return;
}

static struct console mb93403_console = {
	name: "ttyS",
	write: mb93403_console_write
};
#endif /* DEBUG_MB93403_SERIAL */

/*******************************************************************/

static int round_to(int n, int base)
{
    return ((n / base) + ((n / (base / 10)) % 10 >= 5 ? 1: 0)) * base;
}

extern unsigned long frv_proc_khz;
extern char *frv_machine_name;

static void __init fr400pdk2_board_info(void)
{
    frv_proc_khz = 266;
    frv_machine_name = "FR-V Portable Development Kit Ver.2.0";
}

static void __init fr400pdk2_board_meminit(struct meminfo *meminfo)
{
#ifdef NEVER
    unsigned long start;

    if (meminfo->nr_banks == 0) {
	start = (PHYS_OFFSET + PAGE_SIZE - 1) & PAGE_MASK;
	meminfo->nr_banks      = 1;
	meminfo->bank[0].start = start;
	meminfo->bank[0].size  = 0x03000000 - start;
	/* kernel page allocater uses DRAM 48Mbyte (0x00000000 - 0x03000000) */

	/* KERNEL ROM image uses DRAM (0x03800000 - ) */
	/* ROMFS ROM image uses DRAM (0x03c00000 - ) */
    }
#endif
}

#define write_ampr(n, iampr, dampr) \
	do{ \
	    write_spr_register(SPR_IAMPR##n, iampr); \
	    write_spr_register(SPR_DAMPR##n, dampr); \
	}while(0)


static void __init fr400pdk2_board_segtrans_init(void)
{
    unsigned addr, amlr, ampr, v;

/*
  SDRAM bus:
   SCS0#
    0x00000000 - 0x03ffffff  user,  cache,   RW       64M   SDRAM

  Local Bus:
   LCS1#
    0x10000000 - 0x1fffffff  super, nocache, RW      256M   LANC

   LCS2#
    0x20000000 - 0x2fffffff  super, nocache, RW      256M   FPGA

   LCS3#
    0x30000000 - 0x37ffffff  super, nocache, RW      128M   C2 CSR

   LCS5#
    0x38000000 - 0x3fffffff  super, nocache, RW      128M   C2 CSC

  Ext ROM:
   ROM3/4
    0xFD000000 - 0xFDffffff  user, nocache,    RW       16M

*/
    ampr = (0x00000000 & AMPR_PPFN) | AMPR_SS_64M | AMPR_V;
    write_ampr(0, ampr, ampr);

    ampr = (0x10000000 & AMPR_PPFN) | AMPR_SS_256M | AMPR_C | AMPR_S | AMPR_V;
    write_ampr(1, 0, ampr);

    ampr = (0x20000000 & AMPR_PPFN) | AMPR_SS_256M | AMPR_C | AMPR_S | AMPR_V;
    write_ampr(2, 0, ampr);

    ampr = (0x30000000 & AMPR_PPFN) | AMPR_SS_256M | AMPR_C | AMPR_S | AMPR_V;
    write_ampr(3, 0, ampr);

    ampr = (0xfd000000 & AMPR_PPFN) | AMPR_SS_16M | AMPR_C | AMPR_V;
    write_ampr(4, 0, ampr);

    write_ampr(5, 0, 0);
    write_ampr(6, 0, 0);
    write_ampr(7, 0, 0);

    v = read_spr_register(SPR_HSR0);
    v |= (HSR0_EIMMU | HSR0_EDMMU);
    v &= ~HSR0_EMEM;
    write_spr_register(SPR_HSR0,v);
}

static inline void write__pdk2_fpga(u32 x, u16 v)
{
    *((volatile u16 *)(x)) = (v);
    __asm__ __volatile__("membar");
}

void __init fr400pdk2_board_setup(struct meminfo *meminfo)
{
    extern void register_console(struct console *);

    /* setup FPGA for external interrupts */
    write__pdk2_fpga(FR400PDK_2_IRQ_MSK, 0xFFFF); // mask all
    write__pdk2_fpga(FR400PDK_2_IRQ_PND, 0);
    write__pdk2_fpga(FR400PDK_2_IRQ_PRM, 0);

#ifdef CONFIG_SERIAL
	mb93403_uart_init_for_generic_serial_driver();
#endif /* CONFIG_SERIAL */

    fr400pdk2_board_segtrans_init();
    fr400pdk2_board_info();
    fr400pdk2_board_meminit(meminfo);

#ifdef DEBUG_MB93403_SERIAL
    {
	static const char msg[] = "\nWelcome to the MB93403 uart.\n";

	mb93403_uart_init();
	mb93403_console_write(0, msg, sizeof(msg));
	register_console(&mb93403_console);
    }
#endif /* DEBUG_MB93403_SERIAL */
}