flash_setup.c

该程序实现了PAL视频图象在ADI BF533开发板上的动态采集。

/******************************************************************************/
//
// Name: 	BF533 EZ-KIT Flash Driver
//
/******************************************************************************

(C) Copyright 2006 - Analog Devices, Inc.  All rights reserved.

File Name:	Flash_Setup.c

Date Modified:	10/25/04			Rev 0.2

Software:       VisualDSP++4.5

Hardware:		ADSP-BF533 EZ-KIT Board

Special Connections:  None

Purpose:		This driver sets up the ADSP-BF533 EZ-KIT flash
				
				

*********************************************************************************/


#include "flashsetup.h"
#include "system.h"




//Setup of the async interface
void Init_EBIU(void)
{
	
	*pEBIU_AMBCTL0	= 0x7bb07bb0;	// <--|Write access time = 7 cycles, read access time = 11 cycles, no ARDY
	*pEBIU_AMBCTL1	= 0x7bb07bb0;	//    |Hold time = 2 cycles, setup time = 3 cycles, transition time = 4 cycles
	*pEBIU_AMGCTL	= 0x000F;		//	  |Enable all memory banks

}//end Init_EBIU


//To use the GPIOs of the flash it must be initialized
void Init_Flash(void)
{
	*pFlashA_PortA_Out = 0x0;		// clear data registers
	*pFlashA_PortA_Dir = 0xFFFF;	// set dir=output
}//end Init_Flash



//The GPIOs of the flash are linked to the ADV7183 reset pin as well as to the 
//switch that drives the PPI clock. 
void Init_ADV(void)
{
	unsigned char tempReg;
	
	//De-assert the ADV7183 reset and link the ADV7183 Clock "LLC1" to the Blackfin PPI 
	//clock input.
	tempReg = *pFlashA_PortA_Out;
	*pFlashA_PortA_Out = tempReg | RST_7183 | PPICLK_ADV7183_SELECT;


	//Setup the Blackfin PF registers
	
	if ( ((*pDSPID) & 0xFFFF) < 0x2 ) {		// Workaround for anomaly ID# 05000079 for rev 0.1
		tempReg = *pFIO_INEN;
		*pFIO_INEN = tempReg | ADV7183_OE;
	 }
	//Blackfin PF2 pin must be set as output
	tempReg = *pFIO_DIR;
	*pFIO_DIR = tempReg | ADV7183_OE;

	//Set the Blackfin pin PF2 to output enable the ADV7183 data bus		
	tempReg = *pFIO_FLAG_C;
	*pFIO_FLAG_C = tempReg | ADV7183_OE;


}//end Init_ADV