syslib.c

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/* sysLib.c - MagicARM2410 system-dependent routines */


#include "copyright_wrs.h"
#include "vxWorks.h"
#include "config.h"

#include "sysLib.h"
#include "string.h"
#include "intLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "muxLib.h"
#include "cacheLib.h"

#include "arch/arm/mmuArmLib.h"
#include "private/vmLibP.h"
#include "dllLib.h"

/* imports */
IMPORT char end[];			    /* end of system, created by ld */
IMPORT VOIDFUNCPTR _func_armIntStackSplit;  /* ptr to fn to split stack */

#if !defined(INCLUDE_MMU) && \
    (defined(INCLUDE_CACHE_SUPPORT) || defined(INCLUDE_MMU_BASIC) || \
     defined(INCLUDE_MMU_FULL) || defined(INCLUDE_MMU_MPU))
#define INCLUDE_MMU
#endif


#ifdef INCLUDE_LED
#include "sysLed.c"
#endif /* INCLUDE_LED */


/*arm 中断微量初始化*/
		extern void excEnterUndef(void);
		extern void excEnterSwi(void);
		extern void excEnterPrefetchAbort(void);
		extern void excEnterDataAbort(void);
		extern void intEnt(void);
		
		typedef struct {
			UINT32 vector;
			VOIDFUNCPTR func;
			}exc_tbl_t;
		#define SYS_EXC_NUM 5
		LOCAL exc_tbl_t sysExcTbl[SYS_EXC_NUM]={
			{(UINT32)VEC_BASE_ADRS+0x04,(VOIDFUNCPTR)excEnterUndef},
			{(UINT32)VEC_BASE_ADRS+0x08,(VOIDFUNCPTR)excEnterSwi},
			{(UINT32)VEC_BASE_ADRS+0x0c,(VOIDFUNCPTR)excEnterPrefetchAbort},
			{(UINT32)VEC_BASE_ADRS+0x10,(VOIDFUNCPTR)excEnterDataAbort},
			{(UINT32)VEC_BASE_ADRS+0x18,(VOIDFUNCPTR)intEnt}
			};

/* globals */
#if defined(INCLUDE_MMU)
/*
 * The following structure describes the various different parts of the
 * memory map to be used only during initialisation by
 * vm(Base)GlobalMapInit() when INCLUDE_MMU_BASIC/FULL are
 * defined.
 *
 * Clearly, this structure is only needed if the CPU has an MMU!
 *
 * The following are not the smallest areas that could be allocated for a
 * working system. If the amount of memory used by the page tables is
 * critical, they could be reduced.
 */
PHYS_MEM_DESC sysPhysMemDesc [] =
{
	/*
	 * ROM is normally marked as uncacheable by VxWorks. We leave it like that
	 * for the time being, even though this has a severe impact on execution
	 * speed from ROM.
	 */
	{
		(void *) (ROM_BASE_ADRS/*+0xf0000000*/),
		(void *) (ROM_BASE_ADRS),
		ROUND_UP (ROM_SIZE_TOTAL, PAGE_SIZE),
		/*0x200000,*/
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE  | VM_STATE_CACHEABLE_NOT
	}, 	
  /* adrs and length parameters must be page-aligned (multiples of 0x1000) */
    	/* RAM */
	{
		(void *) LOCAL_MEM_LOCAL_ADRS,	/* virtual address */
		(void *) LOCAL_MEM_LOCAL_ADRS,	/* physical address */
		ROUND_UP (LOCAL_MEM_SIZE, PAGE_SIZE), /* length, then initial state: */
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE
	},
	/*
	 * I/O space:
	 * Do not map in all I/O space, only that which has something there.
	 * Otherwise we will use all of RAM allocating page tables!
	 */
	{
		(void *) 0x18000000,		/* DM9000 memey */
		(void *) 0x18000000,
		ROUND_UP (SZ_4M, PAGE_SIZE),
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
	},
	{
		(void *) 0x19000000,		/* CS8900A  io*/
		(void *) 0x19000000,
		ROUND_UP (SZ_4M, PAGE_SIZE),
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
	},
	{
		(void *) 0x48000000,		/* Memory controller */
		(void *) 0x48000000,
		PAGE_SIZE,
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
	},
	{
		(void *) 0x4a000000,		/* Interrupt controller */
		(void *) 0x4a000000,
		PAGE_SIZE,
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
	},
	{
		(void *) 0x4c000000,		/* System & Clock controller */
		(void *) 0x4c000000,
		PAGE_SIZE,
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
	},
	{
		(void *) UART_0_BASE_ADR,	/* UART 0 */
		(void *) UART_0_BASE_ADR,
		PAGE_SIZE,
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
	},
	{
		(void *) UART_1_BASE_ADR,	/* UART 1 */
		(void *) UART_1_BASE_ADR,
		PAGE_SIZE,
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
	},
	{
		(void *) s3c2410x_TIMER_BASE,	/* Timer&Counter */
		(void *) s3c2410x_TIMER_BASE,
		PAGE_SIZE,
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
	},
	{
		(void *) 0x4d000000,             /*LCD controller*/
		(void *) 0x4d000000,
		PAGE_SIZE,
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
  },
	{
		(void *) 0x4e000000,             /* NAND-flash controller */
		(void *) 0x4e000000,
		PAGE_SIZE,
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
	},
	{
		(void *) 0x53000000,		/* WatchDog controller */
		(void *) 0x53000000,
		PAGE_SIZE,
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
	},
	{
		(void *) 0x54000000,		/* IIC controller */
		(void *) 0x54000000,
		PAGE_SIZE,
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
  },
	{
		(void *) 0x56000000,		/* GPIO controller */
		(void *) 0x56000000,
		PAGE_SIZE,
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
	},
	{
		(char *) 0x57000000,		/* Rtc Clock controller */
		(char *) 0x57000000,
		PAGE_SIZE,
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE
	},
	{
		(void *) 0x59000000,		/* SPI controller */
		(void *) 0x59000000,
		PAGE_SIZE,
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
	},
	{
		(void *) 0x58000000,		/* ADC controller */
		(void *) 0x58000000,
		PAGE_SIZE,
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
	}
};

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

#endif /* defined(INCLUDE_MMU) */

int	sysBus	    = BUS;		/* system bus type (VME_BUS, etc) */
int	sysCpu	    = CPU;		/* system CPU type (e.g. ARMARCH4/4_T)*/
char *	sysBootLine = BOOT_LINE_ADRS; 	/* address of boot line */
char *	sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */
int	sysProcNum;			/* processor number of this CPU */
int	sysFlags;			/* boot flags */
char	sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char	sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */


/* locals */

/*
 * List of interrupts to be serviced in order of decreasing priority.
 * Interrupts not in this list will be serviced least-significant bit
 * first at a lower priority than those in the list.
 *
 * To use lowest-bit = highest-priority, reverse the sense of the
 * condition below so that s3c2410xIntLvlPriMap is a zero pointer.
 */

/* defines */


/* externals */

/*
IMPORT int  s3c2410xIntDevInit (void);
*/
IMPORT void sysIntStackSplit (char*, long);


/* globals */


/* forward LOCAL functions declarations */


/* forward declarations */
char *	sysPhysMemTop (void);


/* included source files */
#include "mem/nullNvRam.c"
/*#endif*/
#include "vme/nullVme.c"
#include "s3c2410xIntrCtl.c"
#include "s3c2410xTimer.c"
#include "sysSerial.c"


#ifdef INCLUDE_END
#include "dm9000End.c"
#endif


/*
 * sysModel - return the model name of the CPU board
 *
 * This routine returns the model name of the CPU board.
 *
 * NOTE
 * This routine does not include all of the possible variants, and the
 * inclusion of a variant in here does not mean that it is supported.
 *
 * RETURNS: A pointer to a string identifying the board and CPU.
 */
char* sysModel(void)
{