s3c2410x.h

操作系统中的一找你个的相关的淡淡的码源代码

#define INT_VEC_IIC		      IVEC_TO_INUM(INT_LVL_IIC)
#define INT_VEC_UART_0		  IVEC_TO_INUM(INT_LVL_UART_0)
#define INT_VEC_SPI_1		    IVEC_TO_INUM(INT_LVL_SPI_1)
#define INT_VEC_RTC		      IVEC_TO_INUM(INT_LVL_RTC)
#define INT_VEC_ADC		      IVEC_TO_INUM(INT_LVL_ADC)


/* DMA for s3c2410x */
#define rDISRC0		  (0x4b000000)
#define rDISRC1		  (0x4b000040)
#define rDISRC2		  (0x4b000080)
#define rDISRC3		  (0x4b0000c0)
#define rDISRC_MASK	((1<<31)-1)
#define rDISRCC0	  (0x4b000004)
#define rDISRCC1	  (0x4b000044)
#define rDISRCC2	  (0x4b000084)
#define rDISRCC3	  (0x4b0000c4)
#define rDISRCC_INC_INC		(0<<0)
#define rDISRCC_INC_FIXED	(1<<0)
#define rDISRCC_LOC_AHB		(0<<1)
#define rDISRCC_LOC_APB		(1<<1)
#define rDIDST0		  (0x4b000008)
#define rDIDST1		  (0x4b000048)
#define rDIDST2		  (0x4b000088)
#define rDIDST3		  (0x4b0000c8)
#define rDIDST_MASK	(rDISRC_MASK)
#define rDIDSTC0	  (0x4b00000c)
#define rDIDSTC1	  (0x4b00004c)
#define rDIDSTC2	  (0x4b00008c)
#define rDIDSTC3	  (0x4b0000cc)
#define rDIDSTC_INC_INC		rDISRCC_INC_INC
#define rDIDSTC_INC_FIXED	rDISRCC_INC_FIXED
#define rDIDSTC_LOC_AHB		rDISRCC_LOC_AHB
#define rDIDSTC_LOC_APB		rDISRCC_LOC_APB

#define rDCON0		(0x4b000010)
#define rDCON1		(0x4b000050)
#define rDCON2		(0x4b000090)
#define rDCON3		(0x4b0000d0)

	#define rDCON_TC_MASK	            ((1<<20)-1)
	#define rDCON_DSZ_8	              (0<<20)
	#define rDCON_DSZ_16	            (1<<20)
	#define rDCON_DSZ_32	            (2<<20)
	#define rDCON_RELOAD_AUTO	        (0<<22)
	#define rDCON_RELOAD_OFF	        (1<<22)
	#define rDCON_SE_SW	              (0<<23)
	#define rDCON_SE_HW	              (1<<23)
	#define rDCON0_HWSRCSEL_nXDREQ0	  (0<<24)
	#define rDCON0_HWSRCSEL_UART0	    (1<<24)
	#define rDCON0_HWSRCSEL_SDI	      (2<<24)
	#define rDCON0_HWSRCSEL_TIMER	    (3<<24)
	#define rDCON_HWSRCSEL_USB	      (4<<24)
	#define rDCON1_HWSRCSEL_nXDREQ1	  (0<<24)
	#define rDCON1_HWSRCSEL_UART1	    (1<<24)
	#define rDCON1_HWSRCSEL_I2SSDI	  (2<<24)
	#define rDCON1_HWSRCSEL_SPI	      (3<<24)
	#define rDCON2_HWSRCSEL_I2SSDO	  (0<<24)
	#define rDCON2_HWSRCSEL_I2SSDI	  (1<<24)
	#define rDCON2_HWSRCSEL_SDI	      (2<<24)
	#define rDCON2_HWSRCSEL_TIMER	    (3<<24)
	#define rDCON3_HWSRCSEL_UART2	    (0<<24)
	#define rDCON3_HWSRCSEL_SDI	      (1<<24)
	#define rDCON3_HWSRCSEL_SPI	      (2<<24)
	#define rDCON3_HWSRCSEL_TIMER	    (3<<24)	
	#define rDCON_SERVMODE_SINGLE	    (0<<27)
	#define rDCON_SERVMODE_WHOLE	    (1<<27)
	#define rDCON_TSZ_ONE		          (0<<28)
	#define rDCON_TSZ_FOUR		        (1<<28)
	#define rDCON_INT_OFF		          (0<<29)
	#define rDCON_INT_ON		          (1<<29)
	#define rDCON_SYNC_APB		        (0<<30)
	#define rDCON_SYNC_AHB		        (1<<30)
	#define rDCON_DMD_MODE		        (0<<31)
	#define rDCON_HS_MODE		          (1<<31)
#define rDCSRC0		  (0x4b000018)
#define rDCSRC1		  (0x4b000058)
#define rDCSRC2		  (0x4b000098)
#define rDCSRC3		  (0x4b0000d8)
#define rDCDST0		  (0x4b00001c)
#define rDCDST1		  (0x4b00005c)
#define rDCDST2		  (0x4b00009c)
#define rDCDST3		  (0x4b0000dc)
#define rDMASKTRIG0	(0x4b000020)
#define rDMASKTRIG1	(0x4b000060)
#define rDMASKTRIG2	(0x4b0000a0)
#define rDMASKTRIG3	(0x4b0000e0)

/* definitions for the s3c2410x UART */
#define UART_XTAL_FREQ			      s3c2410x_PCLK	/* UART baud rate clk freq */
#define N_s3c2410x_UART_CHANNELS	2	            /* number of AMBA UART chans */
#define N_SIO_CHANNELS		        N_s3c2410x_UART_CHANNELS
#define N_UART_CHANNELS		        N_s3c2410x_UART_CHANNELS


#define UART_0_BASE_ADR		0x50000000	/* UART 0 base address */
#define UART_1_BASE_ADR		0x50004000	/* UART 1 base address */

/* GPIO PORT */
#define rGPACON    0x56000000    /*Port A control */
#define rGPADAT    0x56000004    /*Port A data */
                        
#define rGPBCON    0x56000010    /*Port B control */
#define rGPBDAT    0x56000014    /*Port B data */
#define rGPBUP     0x56000018    /*Pull-up control B */
                        
#define rGPCCON    0x56000020    /*Port C control */
#define rGPCDAT    0x56000024    /*Port C data */
#define rGPCUP     0x56000028    /*Pull-up control C */
                        
#define rGPDCON    0x56000030    /*Port D control */
#define rGPDDAT    0x56000034    /*Port D data */
#define rGPDUP     0x56000038    /*Pull-up control D */
                        
#define rGPECON    0x56000040    /*Port E control */
#define rGPEDAT    0x56000044    /*Port E data */
#define rGPEUP     0x56000048    /*Pull-up control E */
                        
#define rGPFCON    0x56000050    /*Port F control */
#define rGPFDAT    0x56000054    /*Port F data */
#define rGPFUP     0x56000058    /*Pull-up control F */
                        
#define rGPGCON    0x56000060    /*Port G control */
#define rGPGDAT    0x56000064    /*Port G data */
#define rGPGUP     0x56000068    /*Pull-up control G */
                        
#define rGPHCON    0x56000070    /*Port H control */
#define rGPHDAT    0x56000074    /*Port H data */
#define rGPHUP     0x56000078    /*Pull-up control H */

  #define MASK_GPH10(x)	(x<<20)
	#define MASK_GPH9(x)	(x<<18)
	#define MASK_GPH8(x)	(x<<16)
	#define MASK_GPH7(x)	(x<<14)
	#define MASK_GPH6(x)	(x<<12)
	#define MASK_GPH5(x)	(x<<10)
	#define MASK_GPH4(x)	(x<<8)
	#define MASK_GPH3(x)	(x<<6)
	#define MASK_GPH2(x)	(x<<4)
	#define MASK_GPH1(x)	(x<<2)
	#define MASK_GPH0(x)	(x<<0)
	
#define rMISCCR    0x56000080 /*Miscellaneous control */
#define rDCLKCON   0x56000084 /*DCLK0/1 control */
#define rEXTINT0   0x56000088 /*External interrupt control register 0 */
#define rEXTINT1   0x5600008c /*External interrupt control register 1 */
#define rEXTINT2   0x56000090 /*External interrupt control register 2 */
#define rEINTFLT0  0x56000094 /*Reserved */
#define rEINTFLT1  0x56000098 /*Reserved */
#define rEINTFLT2  0x5600009c /*External interrupt filter control register 2 */
#define rEINTFLT3  0x560000a0 /*External interrupt filter control register 3 */
#define rEINTMASK  0x560000a4 /*External interrupt mask */
#define rEINTPEND  0x560000a8 /*External interrupt pending */
#define rGSTATUS0  0x560000ac /*External pin status */
#define rGSTATUS1  0x560000b0 /*Chip ID(0x32410000) */
#define rGSTATUS2  0x560000b4 /*Reset type */
#define rGSTATUS3  0x560000b8 /*Saved data0(32-bit) before entering POWER_OFF mode */ 
#define rGSTATUS4  0x560000bc /*Saved data0(32-bit) before entering POWER_OFF mode  */

/* definitions for the s3c2410x Timer */
#define s3c2410x_TIMER_BASE		0x51000000	/* Address of base of timer */
#define s3c2410x_TIMER0_BASE ((s3c2410x_TIMER_BASE) + 0x0c)
#define s3c2410x_TIMER1_BASE ((s3c2410x_TIMER_BASE) + 0x18)
#define s3c2410x_TIMER2_BASE ((s3c2410x_TIMER_BASE) + 0x24)
#define s3c2410x_TIMER3_BASE ((s3c2410x_TIMER_BASE) + 0x30)
#define s3c2410x_TIMER4_BASE ((s3c2410x_TIMER_BASE) + 0x3c)

#define SYS_TIMER_BASE s3c2410x_TIMER0_BASE
#define AUX_TIMER_BASE s3c2410x_TIMER1_BASE

#define SYS_TIMER_INT_LVL (INT_LVL_TIMER_0)
#define AUX_TIMER_INT_LVL (INT_LVL_TIMER_1)

#define SYS_TIMER_INT_VEC (INT_VEC_TIMER_0)
#define AUX_TIMER_INT_VEC (INT_VEC_TIMER_1)

#define EINT_0_INT_VEC (INT_VEC_EINT_0)

#define SYS_TIMER_CLK	(s3c2410x_PCLK)
#define AUX_TIMER_CLK	(s3c2410x_PCLK)

/* for timer base */
#define OFFSET_TCFG0	(0x00)
#define OFFSET_TCFG1	(0x04)
#define OFFSET_TCON	  (0x08)
/* for timerX base */
#define OFFSET_TCNTB	(0x00)
#define OFFSET_TCMPB	(0x04)
#define OFFSET_TCNTO	(0x08)

/* Timer clock source frequency = (50*1000000)/(250x2) = 100 000 */
#define TCFG0_INIT_VALUE	(0x0000f9f9)	/* prescaler0..1 = 249 + 1 */
#define TCFG1_INIT_VALUE	(0x00000000)	/* MUX0..4 = 1/2 */

/* bit for TCON */
#define BIT_TIMER0_EN	(1<<0)
#define BIT_TIMER0_MU	(1<<1)
#define BIT_TIMER0_IV	(1<<2)
#define BIT_TIMER0_RE	(1<<3)

#define BIT_TIMER1_EN	(1<<8)
#define BIT_TIMER1_MU	(1<<9)
#define BIT_TIMER1_IV	(1<<10)
#define BIT_TIMER1_RE	(1<<11)

#define BIT_TIMER2_EN	(1<<12)
#define BIT_TIMER2_MU	(1<<13)
#define BIT_TIMER2_IV	(1<<14)
#define BIT_TIMER2_RE	(1<<15)
#define BIT_TIMER3_EN	(1<<16)
#define BIT_TIMER3_MU	(1<<17)
#define BIT_TIMER3_IV	(1<<18)
#define BIT_TIMER3_RE	(1<<19)
#define BIT_TIMER4_EN	(1<<20)
#define BIT_TIMER4_MU	(1<<21)
#define BIT_TIMER4_RE	(1<<22)

#define BIT_SYS_TIMER_EN	BIT_TIMER0_EN
#define BIT_SYS_TIMER_MU	BIT_TIMER0_MU
#define BIT_SYS_TIMER_IV	BIT_TIMER0_IV
#define BIT_SYS_TIMER_RE	BIT_TIMER0_RE

#define BIT_AUX_TIMER_EN	BIT_TIMER1_EN
#define BIT_AUX_TIMER_MU	BIT_TIMER1_MU
#define BIT_AUX_TIMER_IV	BIT_TIMER1_IV
#define BIT_AUX_TIMER_RE	BIT_TIMER1_RE

#define MASTER_TIMER_BASE	s3c2410x_TIMER_BASE
/*------------------------------------------------------------------------------------------------*/
/* Bit field definitions */
#define BIT0                            0x00000001
#define BIT1                            0x00000002
#define BIT2                            0x00000004
#define BIT3                            0x00000008
#define BIT4                            0x00000010
#define BIT5                            0x00000020
#define BIT6                            0x00000040
#define BIT7                            0x00000080
#define BIT8                            0x00000100
#define BIT9                            0x00000200
#define BIT10                           0x00000400
#define BIT11                           0x00000800
#define BIT12                           0x00001000
#define BIT13                           0x00002000
#define BIT14                           0x00004000
#define BIT15                           0x00008000
#define BIT16                           0x00010000
#define BIT17                           0x00020000
#define BIT18                           0x00040000
#define BIT19                           0x00080000
#define BIT20                           0x00100000
#define BIT21				                    0x00200000
#define BIT22				                    0x00400000
#define BIT23				                    0x00800000
#define BIT24				                    0x01000000
#define BIT25				                    0x02000000
#define BIT26				                    0x04000000
#define BIT27				                    0x08000000
#define BIT28				                    0x10000000
#define BIT29				                    0x20000000
#define BIT30				                    0x40000000
#define BIT31				                    0x80000000

/* Handy sizes */

#define SZ_1K                           0x00000400
#define SZ_4K                           0x00001000
#define SZ_8K                           0x00002000
#define SZ_16K                          0x00004000
#define SZ_64K                          0x00010000
#define SZ_128K                         0x00020000
#define SZ_256K                         0x00040000
#define SZ_512K                         0x00080000

#define SZ_1M                           0x00100000
#define SZ_2M                           0x00200000
#define SZ_4M                           0x00400000
#define SZ_8M                           0x00800000
#define SZ_16M                          0x01000000
#define SZ_32M                          0x02000000
#define SZ_64M                          0x04000000
#define SZ_128M                         0x08000000
#define SZ_256M                         0x10000000
#define SZ_512M                         0x20000000

#define SZ_1G                           0x40000000
#define SZ_2G                           0x80000000

#ifdef __cplusplus
}
#endif

#endif	/* INCs3c2410xh */