📄 projmodel.mdl
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OverflowMode "Saturate"
}
Block {
BlockType Reference
Name "DAC2"
Ports [1]
Position [640, 363, 730, 407]
SourceBlock "c6701evmlib/DAC"
SourceType "C6701EVM DAC"
CodecDataFormat "16-bit linear"
Scaling "Normalize"
DacAtten " 0.0"
OverflowMode "Saturate"
}
Block {
BlockType Gain
Name "Gain1\n"
Position [370, 90, 400, 120]
Gain "0.5"
}
Block {
BlockType Gain
Name "Gain2"
Position [375, 190, 405, 220]
Gain "0.5"
}
Block {
BlockType Gain
Name "Gain3"
Position [375, 250, 405, 280]
Gain "0.25"
}
Block {
BlockType Gain
Name "Gain4"
Position [375, 310, 405, 340]
Gain "0.125"
}
Block {
BlockType Gain
Name "Gain5"
Position [295, 405, 325, 435]
Orientation "left"
Gain "0.5"
}
Block {
BlockType Reference
Name "Integer Delay1"
Ports [1, 1]
Position [285, 85, 340, 125]
SourceBlock "dspsigops/Integer Delay"
SourceType "Integer Delay"
delay "4410"
ic "0"
reset_popup "None"
}
Block {
BlockType Reference
Name "Integer Delay2"
Ports [1, 1]
Position [285, 185, 340, 225]
SourceBlock "dspsigops/Integer Delay"
SourceType "Integer Delay"
delay "4410"
ic "0"
reset_popup "None"
}
Block {
BlockType Reference
Name "Integer Delay3"
Ports [1, 1]
Position [285, 245, 340, 285]
SourceBlock "dspsigops/Integer Delay"
SourceType "Integer Delay"
delay "8820"
ic "0"
reset_popup "None"
}
Block {
BlockType Reference
Name "Integer Delay4"
Ports [1, 1]
Position [285, 305, 340, 345]
SourceBlock "dspsigops/Integer Delay"
SourceType "Integer Delay"
delay "13230"
ic "0"
reset_popup "None"
}
Block {
BlockType Reference
Name "Integer Delay5"
Ports [1, 1]
Position [345, 400, 405, 440]
Orientation "left"
SourceBlock "dspsigops/Integer Delay"
SourceType "Integer Delay"
delay "4410"
ic "0"
reset_popup "None"
}
Block {
BlockType Sum
Name "Sum"
Ports [2, 1]
Position [435, 25, 455, 45]
ShowName off
IconShape "round"
Inputs "|++"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum1"
Ports [2, 1]
Position [450, 195, 470, 215]
ShowName off
IconShape "round"
Inputs "|++"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum2"
Ports [2, 1]
Position [435, 255, 455, 275]
ShowName off
IconShape "round"
Inputs "|++"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum3"
Ports [2, 1]
Position [480, 155, 500, 175]
ShowName off
IconShape "round"
Inputs "|++"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType Sum
Name "Sum4"
Ports [2, 1]
Position [260, 375, 280, 395]
ShowName off
IconShape "round"
Inputs "|++"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Line {
SrcBlock "Integer Delay1"
SrcPort 1
DstBlock "Gain1\n"
DstPort 1
}
Line {
SrcBlock "Gain1\n"
SrcPort 1
Points [40, 0]
DstBlock "Sum"
DstPort 2
}
Line {
SrcBlock "ADC"
SrcPort 1
Points [75, 0]
Branch {
DstBlock "Sum"
DstPort 1
}
Branch {
Points [0, 70]
DstBlock "Integer Delay1"
DstPort 1
}
}
Line {
SrcBlock "Integer Delay2"
SrcPort 1
DstBlock "Gain2"
DstPort 1
}
Line {
SrcBlock "Integer Delay3"
SrcPort 1
DstBlock "Gain3"
DstPort 1
}
Line {
SrcBlock "Integer Delay4"
SrcPort 1
DstBlock "Gain4"
DstPort 1
}
Line {
SrcBlock "Gain4"
SrcPort 1
Points [35, 0]
DstBlock "Sum2"
DstPort 2
}
Line {
SrcBlock "Gain3"
SrcPort 1
DstBlock "Sum2"
DstPort 1
}
Line {
SrcBlock "Gain2"
SrcPort 1
DstBlock "Sum1"
DstPort 1
}
Line {
SrcBlock "Sum2"
SrcPort 1
DstBlock "Sum1"
DstPort 2
}
Line {
SrcBlock "Sum1"
SrcPort 1
Points [15, 0]
DstBlock "Sum3"
DstPort 2
}
Line {
Labels [1, 0]
SrcBlock "Sum4"
SrcPort 1
Points [165, 0]
Branch {
Points [0, 35]
DstBlock "Integer Delay5"
DstPort 1
}
Branch {
DstBlock "DAC2"
DstPort 1
}
}
Line {
SrcBlock "Integer Delay5"
SrcPort 1
DstBlock "Gain5"
DstPort 1
}
Line {
SrcBlock "Gain5"
SrcPort 1
Points [-20, 0]
DstBlock "Sum4"
DstPort 2
}
Line {
SrcBlock "Sum"
SrcPort 1
DstBlock "DAC"
DstPort 1
}
Line {
SrcBlock "Sum3"
SrcPort 1
DstBlock "DAC1"
DstPort 1
}
Line {
SrcBlock "ADC1"
SrcPort 1
Points [45, 0]
Branch {
DstBlock "Integer Delay2"
DstPort 1
}
Branch {
Labels [1, 0]
Points [0, 60]
Branch {
DstBlock "Integer Delay3"
DstPort 1
}
Branch {
Points [0, 60]
DstBlock "Integer Delay4"
DstPort 1
}
}
Branch {
Points [0, -40]
DstBlock "Sum3"
DstPort 1
}
}
Line {
SrcBlock "ADC2"
SrcPort 1
DstBlock "Sum4"
DstPort 1
}
}
}
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