mw_c67xx_csl.c

These files are made on MATLAB in which we have got embedded target for C in DSP.

#define _C67XXCHIP_SOURCE_FILE_

#include <stdio.h>
#include <std.h>
#include <csl.h>
#include <csl_edma.h>
#include <csl_mcbsp.h>
    #include <csl_timer.h>
    #include <csl_legacy.h>
#include <csl_irq.h>
#include <csl_cache.h>
#include "MW_c67xx_csl.h"
#include "tmwtypes.h"
#include "projmodel_private.h"

MCBSP_Handle hMcbsp;

    static Uint32 TimerEventId1;
		static TIMER_HANDLE hTimer1;
		
		static UINT32 TimerControl = TIMER_MK_CTL(
          TIMER_CTL_FUNC_GPIO,
          TIMER_CTL_INVOUT_NO,
          TIMER_CTL_DATOUT_0,
          TIMER_CTL_PWID_ONE,
          TIMER_CTL_GO_NO,
          TIMER_CTL_HLD_YES,
          TIMER_CTL_CP_PULSE,
          TIMER_CTL_CLKSRC_CPUOVR4,
          TIMER_CTL_INVINP_NO
		); 

volatile int pendingInterrupt  = FALSE;

    
/* Function: relocate_ISVT() --------------------------------
 *
 * Abstract:
 *      This function relocates ISVT (interrrupt service vector table)
 */

void relocate_ISVT()
{  
    /* Copy ISVT to a new location */	
    memcpy ((void*)0x80000000, (void*)0x0, 0x300);

    /* Set ISTB according to the new address */	
    IRQ_setVecs((void*)0x80000000);
}


    
/* Function: turnOn_L2Cache() --------------------------------
 *
 * Abstract:
 *      This function turns on L2 cache
 */
 
void turnOn_L2Cache()
{  
    /* Turn on 4-way L2 cache and enable caching for CE0 */
    CACHE_setL2Mode (CACHE_64KCACHE);                                          
    CACHE_enableCaching (CACHE_CE00);
}




    
/* Function: Timer1_ISR() -------------------------------------
 *
 * Abstract:
 *      This function services interrupts posted by timer # 1
 */

interrupt void Timer1_ISR () 
{
    pendingInterrupt = TRUE;
    ICR = IFR | 0x8000;
}




/* Function: enable_interrupts -------------------------------
 *
 * Abstract:
 *      Enable the all DMA and DSP interrupts
 */
 
void enable_interrupts()
{ 
	IRQ_nmiEnable();				        /* enable non-maskable interrupts */
	IRQ_globalEnable();				        /* global interrupt enable  */   
        hTimer1 = TIMER_Open(TIMER_DEV1, TIMER_OPEN_RESET); 
        TIMER_ConfigB (hTimer1, 
                       TimerControl,
                       (int) (3.0000000000000000E+005), 
                       0x00000000 
                       );  
    
	TimerEventId1 = TIMER_getEventId(hTimer1);
	IRQ_enable(TimerEventId1);	
        TIMER_start(hTimer1);
    
    ICR = IFR | 0x8000;
    IER |= 0x8002;                        /* enable timer interrupt (# 15)  */
    CSR |= 1;
}



		    
/* Function: mcbsp0_write() ----------------------------------
 *
 * Abstract:
 *      This function writes to McBSP 0
 */
 
void mcbsp0_write (unsigned int out_data)
{
    while( !(MCBSP_xrdy(hMcbsp)));
    MCBSP_write( hMcbsp, out_data );
}



/* Function: mcbsp0_read() -----------------------------------
 *
 * Abstract:
 *      This function reads from McBSP 0
 */
 
unsigned int mcbsp0_read (void)
{
    while(!(MCBSP_rrdy(hMcbsp)));
    return (MCBSP_read(hMcbsp));
}



/* Function: config_McBSP ----------------------------------------------
 *
 * Abstract:
 *      This function configures McBSP 0
 */

void config_McBSP(int port)
{
    hMcbsp = MCBSP_open( MCBSP_DEV0, MCBSP_OPEN_RESET ); 
  
    /* Configure the Serial Port */
    MCBSP_configArgs(
        hMcbsp,
        MCBSP_SPCR_RMK(
        	MCBSP_SPCR_FREE_YES,
        	MCBSP_SPCR_SOFT_NO,
            MCBSP_SPCR_FRST_YES,
            MCBSP_SPCR_GRST_YES,
            MCBSP_SPCR_XINTM_XRDY,
            MCBSP_SPCR_XSYNCERR_NO,
            MCBSP_SPCR_XRST_NO,
            MCBSP_SPCR_DLB_OFF,
            MCBSP_SPCR_RJUST_RZF,
            MCBSP_SPCR_CLKSTP_DISABLE,
            MCBSP_SPCR_DXENA_OFF,
            MCBSP_SPCR_RINTM_RRDY,
            MCBSP_SPCR_RSYNCERR_NO,
            MCBSP_SPCR_RRST_NO     
            ),
        MCBSP_RCR_RMK(
            MCBSP_RCR_RPHASE_SINGLE,
            MCBSP_RCR_RFRLEN2_OF(0),
            MCBSP_RCR_RWDLEN2_8BIT, /* Not using Phase */
            MCBSP_RCR_RCOMPAND_MSB,
            MCBSP_RCR_RFIG_YES,
            MCBSP_RCR_RDATDLY_1BIT,
            MCBSP_RCR_RFRLEN1_OF(0),
            MCBSP_RCR_RWDLEN1_16BIT,
            MCBSP_RCR_RWDREVRS_DISABLE
            ),
        MCBSP_XCR_RMK(
            MCBSP_XCR_XPHASE_SINGLE,
            MCBSP_XCR_XFRLEN2_OF(0),
            MCBSP_XCR_XWDLEN2_8BIT, /* Not using Phase */
            MCBSP_XCR_XCOMPAND_MSB,
            MCBSP_XCR_XFIG_YES,
            MCBSP_XCR_XDATDLY_1BIT,
            MCBSP_XCR_XFRLEN1_OF(0),
            MCBSP_XCR_XWDLEN1_16BIT,
            MCBSP_XCR_XWDREVRS_DISABLE
            ),
        MCBSP_SRGR_DEFAULT,
        MCBSP_MCR_DEFAULT,
        MCBSP_RCER_DEFAULT,
        MCBSP_XCER_DEFAULT,
        MCBSP_PCR_DEFAULT
	);
}

  
			
/* Function: config_DMA ------------------------------------------------
 *
 * Abstract:
 *      This function configures DMA according to the model requirements
 *      (QDMA - Quick Direct Memory Transfer used)
 */
 
void config_DMA(void)
{
	/* General EDMA Initialization */
	EDMA_reset( EDMA_HINV );   /* Clear all pending events              */
	EDMA_RSET(CIER,0x0000);    /* Disable all events to Interrupt       */
	EDMA_RSET(CIPR,0xFFFF);    /* Clear all pending Queued EDMA ints    */
	
    hEdma_xmt			= EDMA_open( EDMA_CHA_XEVT0, 0 );
    hEdma_rcv			= EDMA_open( EDMA_CHA_REVT0, 0 );
    hEdma_rld_ping_rcv	= EDMA_allocTable( -1 );
    hEdma_rld_pong_rcv	= EDMA_allocTable( -1 );
    hEdma_rld_ping_xmt	= EDMA_allocTable( -1 );
    hEdma_rld_pong_xmt	= EDMA_allocTable( -1 );

	/* Initialize EDMA for Transfer from McBSP_0 on Receipt of New Sample	*/
    EDMA_configArgs(
  	  hEdma_rcv,
      EDMA_OPT_RMK(
        EDMA_OPT_PRI_HIGH,
        EDMA_OPT_ESIZE_16BIT,
        EDMA_OPT_2DS_NO,
        EDMA_OPT_SUM_NONE,
        EDMA_OPT_2DD_NO,
        EDMA_OPT_DUM_INC,
        EDMA_OPT_TCINT_YES,
        EDMA_OPT_TCC_OF(0X4),
        EDMA_OPT_LINK_YES,
        EDMA_OPT_FS_NO),
  	  MCBSP_getRcvAddr(hMcbsp),
  	  FRAME_SIZE,
  	  (Uns)&ping_RX[0],
  	  EDMA_IDX_DEFAULT,
  	  EDMA_RLD_RMK( 0,hEdma_rld_pong_rcv )
    );
    
	/* Initialize EDMA Reload Parameters for PingRX Buffer */
    EDMA_configArgs(
  	  hEdma_rld_ping_rcv,
      EDMA_OPT_RMK(
        EDMA_OPT_PRI_HIGH,
        EDMA_OPT_ESIZE_16BIT,
        EDMA_OPT_2DS_NO,
        EDMA_OPT_SUM_NONE,
        EDMA_OPT_2DD_NO,
        EDMA_OPT_DUM_INC,
        EDMA_OPT_TCINT_YES,
        EDMA_OPT_TCC_OF(0X4),
        EDMA_OPT_LINK_YES,
        EDMA_OPT_FS_NO),
  	  MCBSP_getRcvAddr(hMcbsp),
  	  FRAME_SIZE,
  	  (Uns)&ping_RX[0],
  	  EDMA_IDX_DEFAULT,
  	  EDMA_RLD_RMK( 0, hEdma_rld_pong_rcv )
    );
	
	/* Initialize EDMA Reload Parameters for PongRX Buffer */
    EDMA_configArgs(
  	  hEdma_rld_pong_rcv,
      EDMA_OPT_RMK(
        EDMA_OPT_PRI_HIGH,
        EDMA_OPT_ESIZE_16BIT,
        EDMA_OPT_2DS_NO,
        EDMA_OPT_SUM_NONE,
        EDMA_OPT_2DD_NO,
        EDMA_OPT_DUM_INC,
        EDMA_OPT_TCINT_YES,
        EDMA_OPT_TCC_OF(0X5),
        EDMA_OPT_LINK_YES,
        EDMA_OPT_FS_NO),
  	  MCBSP_getRcvAddr(hMcbsp),
  	  FRAME_SIZE,
  	  (Uns)&pong_RX[0],
  	  EDMA_IDX_DEFAULT,
  	  EDMA_RLD_RMK( 0, hEdma_rld_ping_rcv )
    );

	/* Initialize EDMA for Transfer Samples back to McBSP_0 when TXer is Ready */
    EDMA_configArgs(
  	  hEdma_xmt,
      EDMA_OPT_RMK(
        EDMA_OPT_PRI_LOW,
        EDMA_OPT_ESIZE_16BIT,
        EDMA_OPT_2DS_NO,
        EDMA_OPT_SUM_INC,
        EDMA_OPT_2DD_NO,
        EDMA_OPT_DUM_NONE,
        EDMA_OPT_TCINT_YES,
        EDMA_OPT_TCC_OF(0X6),
        EDMA_OPT_LINK_YES,
        EDMA_OPT_FS_NO),
  	  (Uns)&pong_TX[0],
  	  FRAME_SIZE,
  	  MCBSP_getXmtAddr(hMcbsp),
  	  EDMA_IDX_DEFAULT,
  	  EDMA_RLD_RMK( 0, hEdma_rld_ping_xmt )
    );

	/* Initialize EDMA Reload Parameters for PingTX Buffer */
    EDMA_configArgs(
  	  hEdma_rld_ping_xmt,
      EDMA_OPT_RMK(
        EDMA_OPT_PRI_LOW,
        EDMA_OPT_ESIZE_16BIT,
        EDMA_OPT_2DS_NO,
        EDMA_OPT_SUM_INC,
        EDMA_OPT_2DD_NO,
        EDMA_OPT_DUM_NONE,
        EDMA_OPT_TCINT_YES,
        EDMA_OPT_TCC_OF(0X7),
        EDMA_OPT_LINK_YES,
        EDMA_OPT_FS_NO),
  	  (Uns)&ping_TX[0],
  	  FRAME_SIZE,
  	  MCBSP_getXmtAddr(hMcbsp),
  	  EDMA_IDX_DEFAULT,
  	  EDMA_RLD_RMK( 0, hEdma_rld_pong_xmt )
    );

	/* Initialize EDMA Reload Parameters for PongTX Buffer */
	EDMA_configArgs(
  	  hEdma_rld_pong_xmt,
      EDMA_OPT_RMK(
        EDMA_OPT_PRI_LOW,
        EDMA_OPT_ESIZE_16BIT,
        EDMA_OPT_2DS_NO,
        EDMA_OPT_SUM_INC,
        EDMA_OPT_2DD_NO,
        EDMA_OPT_DUM_NONE,
        EDMA_OPT_TCINT_YES,
        EDMA_OPT_TCC_OF(0X6),
        EDMA_OPT_LINK_YES,
        EDMA_OPT_FS_NO),
  	  (Uns)&pong_TX[0],
  	  FRAME_SIZE,
  	  MCBSP_getXmtAddr(hMcbsp),
  	  EDMA_IDX_DEFAULT,
  	  EDMA_RLD_RMK( 0, hEdma_rld_ping_xmt )
    );
	
	EDMA_intEnable(4);
	EDMA_intEnable(5);
	EDMA_intEnable(6);
	EDMA_intEnable(7);

    EDMA_enableChannel( hEdma_xmt );			
    EDMA_enableChannel( hEdma_rcv );
}