simplespi_m.vhdl

Serial pheripheral master

-------------------------------------------------------------------------------
-- Title      : "SPI Master"
-- Project    : 
-------------------------------------------------------------------------------
-- File       : simpleSPI_M.vhdl
-- Author     : Tom Scott www.missiontech.co.nz
-- Company    : Mission Technologies        
-- Created    : 2007-02-05
-- Last update: 2007-05-21
-- Platform   : 
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: Creates a simple SPI Master
-- The master drives the SPI interface providing the Slave Select (SS) to begin
-- data transfer as well as the SCLK to sync data to.
-------------------------------------------------------------------------------
-- Copyright (c) 2007 Mission Technologies
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2007-05-10  1.0      toms    Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-------------------------------------------------------------------------------
entity simpleSPI_M is
  port (
    reset    : in  std_logic;
    clk      : in  std_logic;
    SCLK     : inout std_logic;
    SS       : out std_logic;
    MOSI     : out  std_logic;
    MISO     : in std_logic;
    DataToTx : in std_logic_vector(15 downto 0);
    DataRxd  : out std_logic_vector(15 downto 0);
    StartTx  : in std_logic);
end simpleSPI_M;

architecture a of simpleSPI_M is
    type state_type is (idle, loadData, delay1, txBit, CheckFinished);
    signal state : state_type;

begin
  process(clk, reset, StartTx)

    variable index : integer := 0;
    variable dataLen : integer := 15;   -- this must be set for the length of
                                        -- the data word to be txd
    variable MOSI_v : std_logic;
  begin
    if reset = '1' then
      DataRxd <= (others => '0');  
      SCLK <= '0';
      SS <= '1';
      MOSI_v := 'Z';
      dataLen := 15;
      index := 0;
    else
      if(clk'event and clk = '1') then
        case state is
          when idle =>
            SCLK <= '0';
            SS <= '1';                    -- stop SPI
            MOSI_v :='Z';
            if(StartTx = '1') then
              state <= loadData;
            else
              state <= idle;
              index := 0;
            end if;

          when loadData =>
            SS <= '0';                   -- start SPI
            SCLK <= '0';
            MOSI_v := DataToTx(index);   --set up data to slave
            state <= delay1;

          when delay1 =>
            state <= txBit;
            
          when txBit =>
            SCLK <= '1';
            DataRxd(index) <= MISO;
            state <= CheckFinished;
            
          when checkFinished =>
            if(index = dataLen) then
              state <= idle;
           else
              state <= loadData;
              index := index + 1;
            end if;
          
          when others => null;
        end case;
      end if;
    end if;     
    MOSI <= MOSI_v;
  end process;
end a;