simplespi_m_s.vcd

Serial pheripheral master

$date
  Mon May 21 08:21:23 2007
$end
$version
  GHDL v0
$end
$timescale
  1 fs
$end
$var reg 1 ! reset $end
$var reg 1 " sclk $end
$var reg 1 # ss $end
$var reg 1 $ mosi $end
$var reg 1 % miso $end
$var reg 16 & datatotx_m[15:0] $end
$var reg 16 ' datarxd_m[15:0] $end
$var reg 16 ( datatotx_s[15:0] $end
$var reg 16 ) datarxd_s[15:0] $end
$var reg 1 * starttx $end
$var reg 1 + clk $end
$scope module dut1 $end
$var reg 1 , reset $end
$var reg 1 - clk $end
$var reg 1 . sclk $end
$var reg 1 / ss $end
$var reg 1 0 mosi $end
$var reg 1 1 miso $end
$var reg 16 2 datatotx[15:0] $end
$var reg 16 3 datarxd[15:0] $end
$var reg 1 4 starttx $end
$comment state is not handled $end
$upscope $end
$scope module dut2 $end
$var reg 1 5 reset $end
$var reg 1 6 clk $end
$var reg 1 7 sclk $end
$var reg 1 8 ss $end
$var reg 1 9 mosi $end
$var reg 1 : miso $end
$var reg 16 ; datatotx[15:0] $end
$var reg 16 < datarxd[15:0] $end
$comment state is not handled $end
$var reg 1 = sclk_old $end
$var reg 1 > ss_old $end
$upscope $end
$enddefinitions $end
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#3070000000
0+
0-
06
#3080000000
1+
1-
16
#3090000000
0+
0-
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#3100000000
1+
1-
16
#3110000000
0+
0-
06
#3120000000
1+
1-
16
#3130000000
0+
0-
06
#3140000000
1+
1-
16
#3150000000
0+
0-
06
#3160000000
1+
1-
16
#3170000000
0+
0-
06
#3180000000
1+
1-
16
#3190000000
0+
0-
06
#3200000000
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#3210000000
0+
0-
06
#3220000000
1+
1-
16
#3230000000
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#3240000000
1+
1-
16
#3250000000
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#3260000000
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#3270000000
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#3280000000
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#3290000000
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0-
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#3300000000
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#3310000000
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#3320000000
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#3330000000
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#3340000000
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b1111111110101010 &
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