simplespi_m_s_tb.vhdl

Serial pheripheral master

-------------------------------------------------------------------------------
-- Title      : Testbench for design "simpleSPI"
-- Project    : 
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-- File       : simpleSPI_M_S_tb.vhdl
-- Author     : Tom Scott
-- Company    : www.missiontech.co.nz
-- Created    : 2007-05-15
-- Last update: 2007-05-21
-- Platform   : 
-- Standard   : VHDL'87
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-- Description: Simple SPI master, slave
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-- Copyright (c) 2007 Mission Technologies
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2007-05-15  1.0      toms	Created
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library ieee;
use ieee.std_logic_1164.all;

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entity simpleSPI_M_S_tb is

end simpleSPI_M_S_tb;

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architecture a of simpleSPI_M_S_tb is

  component simpleSPI_M
    port (
      reset    : in  std_logic;
      clk      : in  std_logic;
      SCLK     : inout std_logic;
      SS       : out std_logic;
      MOSI     : out std_logic;
      MISO     : in  std_logic;
      DataToTx : in  std_logic_vector(15 downto 0);
      DataRxd  : out std_logic_vector(15 downto 0);
      StartTx  : in  std_logic
      );
  end component;

  component simpleSPI_S
    port (
      reset    : in  std_logic;
      clk      : in  std_logic;
      SCLK     : in  std_logic;
      SS       : in  std_logic;
      MOSI     : in  std_logic;
      MISO     : out std_logic;
      DataToTx : in  std_logic_vector(15 downto 0);
      DataRxd  : out std_logic_vector(15 downto 0)
      );
  end component;

  -- component ports
  signal reset    : std_logic;
  signal SCLK     : std_logic;
  signal SS       : std_logic;
  signal MOSI     : std_logic;
  signal MISO     : std_logic;
  signal DataToTx_M : std_logic_vector(15 downto 0);
  signal DataRxd_M  : std_logic_vector(15 downto 0);
  signal DataToTx_S : std_logic_vector(15 downto 0);
  signal DataRxd_S  : std_logic_vector(15 downto 0);
  signal StartTx : std_logic;

  -- clock
  signal clk : std_logic := '1';

begin  -- a

  -- component instantiation
  DUT1: simpleSPI_M
    port map (
      reset    => reset,
      clk      => clk,
      SCLK     => SCLK,
      SS       => SS,
      MOSI     => MOSI,
      MISO     => MISO,
      DataToTx => DataToTx_M,
      DataRxd  => DataRxd_M,
      StartTx  => StartTx);

  DUT2: simpleSPI_S
    port map (
      reset    => reset,
      clk      => clk,
      SCLK     => SCLK,
      SS       => SS,
      MOSI     => MOSI,
      MISO     => MISO,
      DataToTx => DataToTx_S,
      DataRxd  => DataRxd_S);

  -- clock generation
  clk <= not clk after 10 ns;

  -- waveform generation
  WaveGen_Proc: process
  begin
    -- insert signal assignments here
  reset <= '1';
  StartTx <= '0';
  DataToTx_M <= "0101010101010101";
  DataToTx_S <= "1010101010101010";
  wait until Clk = '1';
  reset <= '0';
  wait until Clk = '1';
  StartTx <= '1';
  wait until Clk = '1';
  StartTx <= '0';

  for i in 0 to 80 loop
    wait until Clk = '1';
  end loop;  -- i

  DataToTx_M <= "1010101010101010";
  DataToTx_S <= "0101010101010101";
  wait until Clk = '1';
  StartTx <= '1';
  wait until Clk = '1';
  StartTx <= '0';
  wait until Clk = '1';

  for i in 0 to 80 loop
    wait until Clk = '1';
  end loop;  -- i

  DataToTx_M <= "1111111110101010";
  DataToTx_S <= "0101010101111111";
  wait until Clk = '1';
  StartTx <= '1';
  wait until Clk = '1';
  StartTx <= '0';
  wait until Clk = '1';

  for i in 0 to 80 loop
    wait until Clk = '1';
  end loop;  -- i

  DataToTx_S <= "1111111110101010";
  DataToTx_M <= "0101010101111111";
  wait until Clk = '1';
  StartTx <= '1';
  wait until Clk = '1';
  StartTx <= '0';
  wait until Clk = '1';
  
  report "Finished" severity warning;
  wait;
  end process WaveGen_Proc;

  

end a;

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configuration simpleSPI_M_S_tb_a_cfg of simpleSPI_M_S_tb is
  for a
  end for;
end simpleSPI_M_S_tb_a_cfg;

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